ENGR00118204 Update power related register header file

register header file is created from xml file.
some register use related address but some one not.

Signed-off-by: Frank.Li <Frank.Li@freescale.com>

4 files changed, 1941 insertions, 357 deletions

diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
index 08f26f1424cd..86842de91a3c 100644
--- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
@@ -1,7 +1,7 @@
 /*
- * stmp378x: CLKCTRL register definitions
+ * STMP CLKCTRL Register Definitions
  *
- * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,106 +17,447 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
  */
-#ifndef _MACH_REGS_CLKCTRL
-#define _MACH_REGS_CLKCTRL
 
-#define REGS_CLKCTRL_BASE	(STMP3XXX_REGS_BASE + 0x40000)
-#define REGS_CLKCTRL_PHYS	0x80040000
-#define REGS_CLKCTRL_SIZE	0x2000
+#ifndef __ARCH_ARM___CLKCTRL_H
+#define __ARCH_ARM___CLKCTRL_H  1
+
+#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
+#define REGS_CLKCTRL_PHYS (0x80040000)
+#define REGS_CLKCTRL_SIZE 0x00002000
 
-#define HW_CLKCTRL_PLLCTRL0	0x0
+#define HW_CLKCTRL_PLLCTRL0	(0x00000000)
+#define HW_CLKCTRL_PLLCTRL0_SET	(0x00000004)
+#define HW_CLKCTRL_PLLCTRL0_CLR	(0x00000008)
+#define HW_CLKCTRL_PLLCTRL0_TOG	(0x0000000c)
+#define HW_CLKCTRL_PLLCTRL0_ADDR	(REGS_CLKCTRL_BASE + 0x00000000)
+
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6	30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6	0xC0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
+		(((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL	28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL	0x30000000
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
+		(((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5	26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5	0x0C000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)  \
+		(((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL	24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL	0x03000000
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
+		(((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4	22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4	0x00C00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)  \
+		(((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL	20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL	0x00300000
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
+		(((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3	0x00080000
 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS	0x00040000
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2	0x00020000
 #define BM_CLKCTRL_PLLCTRL0_POWER	0x00010000
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1	0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1	0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)  \
+		(((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
 
-#define HW_CLKCTRL_CPU		0x20
-#define BM_CLKCTRL_CPU_DIV_CPU	0x0000003F
-#define BP_CLKCTRL_CPU_DIV_CPU	0
+#define HW_CLKCTRL_PLLCTRL1	(0x00000010)
+#define HW_CLKCTRL_PLLCTRL1_ADDR	(REGS_CLKCTRL_BASE + 0x00000010)
+
+#define BM_CLKCTRL_PLLCTRL1_LOCK	0x80000000
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK	0x40000000
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1	16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1	0x3FFF0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)  \
+		(((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT	0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT	0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
+		(((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_CPU	(0x00000020)
+#define HW_CLKCTRL_CPU_SET	(0x00000024)
+#define HW_CLKCTRL_CPU_CLR	(0x00000028)
+#define HW_CLKCTRL_CPU_TOG	(0x0000002c)
+#define HW_CLKCTRL_CPU_ADDR	(REGS_CLKCTRL_BASE + 0x00000020)
+
+#define BP_CLKCTRL_CPU_RSRVD5	30
+#define BM_CLKCTRL_CPU_RSRVD5	0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+		(((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL	0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU	0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4	0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN	0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL	16
+#define BM_CLKCTRL_CPU_DIV_XTAL	0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
+		(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3	13
+#define BM_CLKCTRL_CPU_RSRVD3	0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v)  \
+		(((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT	0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2	0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN	0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1	6
+#define BM_CLKCTRL_CPU_RSRVD1	0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v)  \
+		(((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU	0
+#define BM_CLKCTRL_CPU_DIV_CPU	0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
+		(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
 
-#define HW_CLKCTRL_HBUS		0x30
-#define BM_CLKCTRL_HBUS_DIV	0x0000001F
-#define BP_CLKCTRL_HBUS_DIV	0
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN	0x00000020
+#define HW_CLKCTRL_HBUS	(0x00000030)
+#define HW_CLKCTRL_HBUS_SET	(0x00000034)
+#define HW_CLKCTRL_HBUS_CLR	(0x00000038)
+#define HW_CLKCTRL_HBUS_TOG	(0x0000003c)
+#define HW_CLKCTRL_HBUS_ADDR	(REGS_CLKCTRL_BASE + 0x00000030)
+
+#define BP_CLKCTRL_HBUS_RSRVD4	30
+#define BM_CLKCTRL_HBUS_RSRVD4	0xC0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v) \
+		(((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
 #define BM_CLKCTRL_HBUS_BUSY	0x20000000
 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE	0x10000000
 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE	0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE	0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE	0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE	0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE	0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	0x00200000
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE	0x00100000
+#define BM_CLKCTRL_HBUS_RSRVD2	0x00080000
 #define BP_CLKCTRL_HBUS_SLOW_DIV	16
 #define BM_CLKCTRL_HBUS_SLOW_DIV	0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v) 	\
-	(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1	0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2	0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4	0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8	0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16	0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32	0x5
-#define BF_CLKCTRL_HBUS_DIV(v)		\
-	(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS		0x40
-
-#define HW_CLKCTRL_XTAL		0x50
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE	0x10000000
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
+		(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1	6
+#define BM_CLKCTRL_HBUS_RSRVD1	0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
+		(((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN	0x00000020
+#define BP_CLKCTRL_HBUS_DIV	0
+#define BM_CLKCTRL_HBUS_DIV	0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+
+#define HW_CLKCTRL_XBUS	(0x00000040)
+#define HW_CLKCTRL_XBUS_ADDR	(REGS_CLKCTRL_BASE + 0x00000040)
+
+#define BM_CLKCTRL_XBUS_BUSY	0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1	11
+#define BM_CLKCTRL_XBUS_RSRVD1	0x7FFFF800
+#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
+		(((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN	0x00000400
+#define BP_CLKCTRL_XBUS_DIV	0
+#define BM_CLKCTRL_XBUS_DIV	0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+
+#define HW_CLKCTRL_XTAL	(0x00000050)
+#define HW_CLKCTRL_XTAL_SET	(0x00000054)
+#define HW_CLKCTRL_XTAL_CLR	(0x00000058)
+#define HW_CLKCTRL_XTAL_TOG	(0x0000005c)
+#define HW_CLKCTRL_XTAL_ADDR	(REGS_CLKCTRL_BASE + 0x00000050)
+
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE	0x80000000
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE	0x40000000
 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE	0x20000000
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE	0x10000000
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE	0x08000000
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE	0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1	2
+#define BM_CLKCTRL_XTAL_RSRVD1	0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
+		(((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART	0
+#define BM_CLKCTRL_XTAL_DIV_UART	0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
+		(((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+
+#define HW_CLKCTRL_PIX	(0x00000060)
+#define HW_CLKCTRL_PIX_ADDR	(REGS_CLKCTRL_BASE + 0x00000060)
 
-#define HW_CLKCTRL_PIX		0x60
-#define BM_CLKCTRL_PIX_DIV	0x00000FFF
-#define BP_CLKCTRL_PIX_DIV	0
 #define BM_CLKCTRL_PIX_CLKGATE	0x80000000
+#define BM_CLKCTRL_PIX_RSRVD2	0x40000000
+#define BM_CLKCTRL_PIX_BUSY	0x20000000
+#define BP_CLKCTRL_PIX_RSRVD1	13
+#define BM_CLKCTRL_PIX_RSRVD1	0x1FFFE000
+#define BF_CLKCTRL_PIX_RSRVD1(v)  \
+		(((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN	0x00001000
+#define BP_CLKCTRL_PIX_DIV	0
+#define BM_CLKCTRL_PIX_DIV	0x00000FFF
+#define BF_CLKCTRL_PIX_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_PIX_DIV)
+
+#define HW_CLKCTRL_SSP	(0x00000070)
+#define HW_CLKCTRL_SSP_ADDR	(REGS_CLKCTRL_BASE + 0x00000070)
+
+#define BM_CLKCTRL_SSP_CLKGATE	0x80000000
+#define BM_CLKCTRL_SSP_RSRVD2	0x40000000
+#define BM_CLKCTRL_SSP_BUSY	0x20000000
+#define BP_CLKCTRL_SSP_RSRVD1	10
+#define BM_CLKCTRL_SSP_RSRVD1	0x1FFFFC00
+#define BF_CLKCTRL_SSP_RSRVD1(v)  \
+		(((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN	0x00000200
+#define BP_CLKCTRL_SSP_DIV	0
+#define BM_CLKCTRL_SSP_DIV	0x000001FF
+#define BF_CLKCTRL_SSP_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_SSP_DIV)
+
+#define HW_CLKCTRL_GPMI	(0x00000080)
+#define HW_CLKCTRL_GPMI_ADDR	(REGS_CLKCTRL_BASE + 0x00000080)
+
+#define BM_CLKCTRL_GPMI_CLKGATE	0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2	0x40000000
+#define BM_CLKCTRL_GPMI_BUSY	0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1	11
+#define BM_CLKCTRL_GPMI_RSRVD1	0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
+		(((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN	0x00000400
+#define BP_CLKCTRL_GPMI_DIV	0
+#define BM_CLKCTRL_GPMI_DIV	0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_GPMI_DIV)
 
-#define HW_CLKCTRL_SSP		0x70
+#define HW_CLKCTRL_SPDIF	(0x00000090)
+#define HW_CLKCTRL_SPDIF_ADDR	(REGS_CLKCTRL_BASE + 0x00000090)
 
-#define HW_CLKCTRL_GPMI		0x80
+#define BM_CLKCTRL_SPDIF_CLKGATE	0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD	0
+#define BM_CLKCTRL_SPDIF_RSRVD	0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
+		(((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
 
-#define HW_CLKCTRL_SPDIF	0x90
+#define HW_CLKCTRL_EMI	(0x000000a0)
+#define HW_CLKCTRL_EMI_ADDR	(REGS_CLKCTRL_BASE + 0x000000a0)
 
-#define HW_CLKCTRL_EMI		0xA0
 #define BM_CLKCTRL_EMI_CLKGATE	0x80000000
-#define BM_CLKCTRL_EMI_DIV_EMI	0x0000003F
-#define BP_CLKCTRL_EMI_DIV_EMI	0
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE	0x00010000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC	0x00020000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI	0x10000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN	0x40000000
 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL	0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI	0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU	0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE	0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3	18
+#define BM_CLKCTRL_EMI_RSRVD3	0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)  \
+		(((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC	0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE	0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2	12
+#define BM_CLKCTRL_EMI_RSRVD2	0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v)  \
+		(((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL	8
+#define BM_CLKCTRL_EMI_DIV_XTAL	0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
+		(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1	6
+#define BM_CLKCTRL_EMI_RSRVD1	0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v)  \
+		(((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI	0
+#define BM_CLKCTRL_EMI_DIV_EMI	0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
+		(((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
 
-#define HW_CLKCTRL_IR		0xB0
+#define HW_CLKCTRL_IR	(0x000000b0)
+#define HW_CLKCTRL_IR_ADDR	(REGS_CLKCTRL_BASE + 0x000000b0)
 
-#define HW_CLKCTRL_SAIF		0xC0
+#define BM_CLKCTRL_IR_CLKGATE	0x80000000
+#define BM_CLKCTRL_IR_RSRVD3	0x40000000
+#define BM_CLKCTRL_IR_AUTO_DIV	0x20000000
+#define BM_CLKCTRL_IR_IR_BUSY	0x10000000
+#define BM_CLKCTRL_IR_IROV_BUSY	0x08000000
+#define BP_CLKCTRL_IR_RSRVD2	25
+#define BM_CLKCTRL_IR_RSRVD2	0x06000000
+#define BF_CLKCTRL_IR_RSRVD2(v)  \
+		(((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
+#define BP_CLKCTRL_IR_IROV_DIV	16
+#define BM_CLKCTRL_IR_IROV_DIV	0x01FF0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)  \
+		(((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
+#define BP_CLKCTRL_IR_RSRVD1	10
+#define BM_CLKCTRL_IR_RSRVD1	0x0000FC00
+#define BF_CLKCTRL_IR_RSRVD1(v)  \
+		(((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
+#define BP_CLKCTRL_IR_IR_DIV	0
+#define BM_CLKCTRL_IR_IR_DIV	0x000003FF
+#define BF_CLKCTRL_IR_IR_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
 
-#define HW_CLKCTRL_TV		0xD0
+#define HW_CLKCTRL_SAIF	(0x000000c0)
+#define HW_CLKCTRL_SAIF_ADDR	(REGS_CLKCTRL_BASE + 0x000000c0)
 
-#define HW_CLKCTRL_ETM		0xE0
+#define BM_CLKCTRL_SAIF_CLKGATE	0x80000000
+#define BM_CLKCTRL_SAIF_RSRVD2	0x40000000
+#define BM_CLKCTRL_SAIF_BUSY	0x20000000
+#define BP_CLKCTRL_SAIF_RSRVD1	17
+#define BM_CLKCTRL_SAIF_RSRVD1	0x1FFE0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v)  \
+		(((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN	0x00010000
+#define BP_CLKCTRL_SAIF_DIV	0
+#define BM_CLKCTRL_SAIF_DIV	0x0000FFFF
+#define BF_CLKCTRL_SAIF_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_SAIF_DIV)
 
-#define HW_CLKCTRL_FRAC		0xF0
-#define BM_CLKCTRL_FRAC_EMIFRAC	0x00003F00
-#define BP_CLKCTRL_FRAC_EMIFRAC	8
-#define BM_CLKCTRL_FRAC_PIXFRAC	0x003F0000
-#define BP_CLKCTRL_FRAC_PIXFRAC	16
+#define HW_CLKCTRL_TV	(0x000000d0)
+#define HW_CLKCTRL_TV_ADDR	(REGS_CLKCTRL_BASE + 0x000000d0)
+
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE	0x80000000
+#define BM_CLKCTRL_TV_CLK_TV_GATE	0x40000000
+#define BP_CLKCTRL_TV_RSRVD	0
+#define BM_CLKCTRL_TV_RSRVD	0x3FFFFFFF
+#define BF_CLKCTRL_TV_RSRVD(v)  \
+		(((v) << 0) & BM_CLKCTRL_TV_RSRVD)
+
+#define HW_CLKCTRL_ETM	(0x000000e0)
+#define HW_CLKCTRL_ETM_ADDR	(REGS_CLKCTRL_BASE + 0x000000e0)
+
+#define BM_CLKCTRL_ETM_CLKGATE	0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2	0x40000000
+#define BM_CLKCTRL_ETM_BUSY	0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1	7
+#define BM_CLKCTRL_ETM_RSRVD1	0x1FFFFF80
+#define BF_CLKCTRL_ETM_RSRVD1(v)  \
+		(((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN	0x00000040
+#define BP_CLKCTRL_ETM_DIV	0
+#define BM_CLKCTRL_ETM_DIV	0x0000003F
+#define BF_CLKCTRL_ETM_DIV(v)  \
+		(((v) << 0) & BM_CLKCTRL_ETM_DIV)
+
+#define HW_CLKCTRL_FRAC	(0x000000f0)
+#define HW_CLKCTRL_FRAC_SET	(0x000000f4)
+#define HW_CLKCTRL_FRAC_CLR	(0x000000f8)
+#define HW_CLKCTRL_FRAC_TOG	(0x000000fc)
+#define HW_CLKCTRL_FRAC_ADDR	(REGS_CLKCTRL_BASE + 0x000000f0)
+
+#define BM_CLKCTRL_FRAC_CLKGATEIO	0x80000000
+#define BM_CLKCTRL_FRAC_IO_STABLE	0x40000000
+#define BP_CLKCTRL_FRAC_IOFRAC	24
+#define BM_CLKCTRL_FRAC_IOFRAC	0x3F000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
+		(((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
 #define BM_CLKCTRL_FRAC_CLKGATEPIX	0x00800000
+#define BM_CLKCTRL_FRAC_PIX_STABLE	0x00400000
+#define BP_CLKCTRL_FRAC_PIXFRAC	16
+#define BM_CLKCTRL_FRAC_PIXFRAC	0x003F0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
+		(((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
+#define BM_CLKCTRL_FRAC_CLKGATEEMI	0x00008000
+#define BM_CLKCTRL_FRAC_EMI_STABLE	0x00004000
+#define BP_CLKCTRL_FRAC_EMIFRAC	8
+#define BM_CLKCTRL_FRAC_EMIFRAC	0x00003F00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
+		(((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
+#define BM_CLKCTRL_FRAC_CLKGATECPU	0x00000080
+#define BM_CLKCTRL_FRAC_CPU_STABLE	0x00000040
+#define BP_CLKCTRL_FRAC_CPUFRAC	0
+#define BM_CLKCTRL_FRAC_CPUFRAC	0x0000003F
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
+		(((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
 
-#define HW_CLKCTRL_FRAC1	0x100
+#define HW_CLKCTRL_FRAC1	(0x00000100)
+#define HW_CLKCTRL_FRAC1_SET	(0x00000104)
+#define HW_CLKCTRL_FRAC1_CLR	(0x00000108)
+#define HW_CLKCTRL_FRAC1_TOG	(0x0000010c)
+#define HW_CLKCTRL_FRAC1_ADDR	(REGS_CLKCTRL_BASE + 0x00000100)
 
-#define HW_CLKCTRL_CLKSEQ	0x110
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX	0x00000002
+#define BM_CLKCTRL_FRAC1_CLKGATEVID	0x80000000
+#define BM_CLKCTRL_FRAC1_VID_STABLE	0x40000000
+#define BP_CLKCTRL_FRAC1_RSRVD1	0
+#define BM_CLKCTRL_FRAC1_RSRVD1	0x3FFFFFFF
+#define BF_CLKCTRL_FRAC1_RSRVD1(v)  \
+		(((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
+
+#define HW_CLKCTRL_CLKSEQ	(0x00000110)
+#define HW_CLKCTRL_CLKSEQ_SET	(0x00000114)
+#define HW_CLKCTRL_CLKSEQ_CLR	(0x00000118)
+#define HW_CLKCTRL_CLKSEQ_TOG	(0x0000011c)
+#define HW_CLKCTRL_CLKSEQ_ADDR	(REGS_CLKCTRL_BASE + 0x00000110)
+
+#define BP_CLKCTRL_CLKSEQ_RSRVD1	9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1	0xFFFFFE00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
+		(((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM	0x00000100
 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU	0x00000080
 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI	0x00000040
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP	0x00000020
 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI	0x00000010
 #define BM_CLKCTRL_CLKSEQ_BYPASS_IR	0x00000008
+#define BM_CLKCTRL_CLKSEQ_RSRVD0	0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX	0x00000002
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF	0x00000001
 
-#define HW_CLKCTRL_RESET	0x120
+#define HW_CLKCTRL_RESET	(0x00000120)
+#define HW_CLKCTRL_RESET_ADDR	(REGS_CLKCTRL_BASE + 0x00000120)
+
+#define BP_CLKCTRL_RESET_RSRVD	2
+#define BM_CLKCTRL_RESET_RSRVD	0xFFFFFFFC
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+		(((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_CHIP	0x00000002
 #define BM_CLKCTRL_RESET_DIG	0x00000001
-#define BP_CLKCTRL_RESET_DIG	0
 
-#endif
+#define HW_CLKCTRL_STATUS	(0x00000130)
+#define HW_CLKCTRL_STATUS_ADDR	(REGS_CLKCTRL_BASE + 0x00000130)
+
+#define BP_CLKCTRL_STATUS_CPU_LIMIT	30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT	0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+		(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD	0
+#define BM_CLKCTRL_STATUS_RSRVD	0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v)  \
+		(((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+
+#define HW_CLKCTRL_VERSION	(0x00000140)
+#define HW_CLKCTRL_VERSION_ADDR	(REGS_CLKCTRL_BASE + 0x00000140)
+
+#define BP_CLKCTRL_VERSION_MAJOR	24
+#define BM_CLKCTRL_VERSION_MAJOR	0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR	16
+#define BM_CLKCTRL_VERSION_MINOR	0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP	0
+#define BM_CLKCTRL_VERSION_STEP	0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v)  \
+		(((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+#endif /* __ARCH_ARM___CLKCTRL_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
index 5293005523b3..1add4b46e22e 100644
--- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
@@ -1,7 +1,7 @@
 /*
- * stmp378x: DIGCTL register definitions
+ * STMP DIGCTL Register Definitions
  *
- * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,22 +17,763 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
  */
-#define REGS_DIGCTL_BASE	(STMP3XXX_REGS_BASE + 0x1C000)
-#define REGS_DIGCTL_PHYS	0x8001C000
-#define REGS_DIGCTL_SIZE	0x2000
 
-#define HW_DIGCTL_CTRL		0x0
+#ifndef __ARCH_ARM___DIGCTL_H
+#define __ARCH_ARM___DIGCTL_H  1
+
+#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1c000)
+#define REGS_DIGCTL_PHYS (0x8001C000)
+#define REGS_DIGCTL_SIZE 0x00002000
+
+#define HW_DIGCTL_CTRL	(0x00000000)
+#define HW_DIGCTL_CTRL_SET	(0x00000004)
+#define HW_DIGCTL_CTRL_CLR	(0x00000008)
+#define HW_DIGCTL_CTRL_TOG	(0x0000000c)
+#define HW_DIGCTL_CTRL_ADDR	(REGS_DIGCTL_BASE + 0x00000000)
+
+#define BM_DIGCTL_CTRL_RSVD3	0x80000000
+#define BM_DIGCTL_CTRL_XTAL24M_GATE	0x40000000
+#define BM_DIGCTL_CTRL_TRAP_IRQ	0x20000000
+#define BP_DIGCTL_CTRL_RSVD2	27
+#define BM_DIGCTL_CTRL_RSVD2	0x18000000
+#define BF_DIGCTL_CTRL_RSVD2(v)  \
+		(((v) << 27) & BM_DIGCTL_CTRL_RSVD2)
+#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE	0x04000000
+#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN	0x02000000
+#define BM_DIGCTL_CTRL_LCD_BIST_START	0x01000000
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN	0x00800000
+#define BM_DIGCTL_CTRL_DCP_BIST_START	0x00400000
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN	0x00200000
+#define BM_DIGCTL_CTRL_USB_TESTMODE	0x00100000
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE	0x00080000
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE	0x00040000
+#define BM_DIGCTL_CTRL_ARM_BIST_START	0x00020000
+#define BM_DIGCTL_CTRL_UART_LOOPBACK	0x00010000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK	0x00008000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL	13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL	0x00006000
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)  \
+		(((v) << 13) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL)
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL	0x00001000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL	0x00000800
+#define BM_DIGCTL_CTRL_RSVD1	0x00000400
+#define BM_DIGCTL_CTRL_SY_ENDIAN	0x00000200
+#define BM_DIGCTL_CTRL_SY_SFTRST	0x00000100
+#define BM_DIGCTL_CTRL_SY_CLKGATE	0x00000080
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG	0x00000040
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG    0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE	0x00000020
+#define BM_DIGCTL_CTRL_TRAP_ENABLE	0x00000010
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE	0x00000008
 #define BM_DIGCTL_CTRL_USB_CLKGATE	0x00000004
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD	0x00000002
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL     0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY	0x00000001
 
-#define HW_DIGCTL_ARMCACHE	0x2B0
-#define BM_DIGCTL_ARMCACHE_ITAG_SS	0x00000003
-#define BP_DIGCTL_ARMCACHE_ITAG_SS	0
-#define BM_DIGCTL_ARMCACHE_DTAG_SS	0x00000030
-#define BP_DIGCTL_ARMCACHE_DTAG_SS	4
-#define BM_DIGCTL_ARMCACHE_CACHE_SS	0x00000300
-#define BP_DIGCTL_ARMCACHE_CACHE_SS	8
-#define BM_DIGCTL_ARMCACHE_DRTY_SS	0x00003000
-#define BP_DIGCTL_ARMCACHE_DRTY_SS	12
-#define BM_DIGCTL_ARMCACHE_VALID_SS	0x00030000
+#define HW_DIGCTL_STATUS	(0x00000010)
+#define HW_DIGCTL_STATUS_SET	(0x00000014)
+#define HW_DIGCTL_STATUS_CLR	(0x00000018)
+#define HW_DIGCTL_STATUS_TOG	(0x0000001c)
+#define HW_DIGCTL_STATUS_ADDR	(REGS_DIGCTL_BASE + 0x00000010)
+
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT	0x80000000
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT	0x40000000
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT	0x20000000
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT	0x10000000
+#define BP_DIGCTL_STATUS_RSVD2	11
+#define BM_DIGCTL_STATUS_RSVD2	0x0FFFF800
+#define BF_DIGCTL_STATUS_RSVD2(v)  \
+		(((v) << 11) & BM_DIGCTL_STATUS_RSVD2)
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL	0x00000400
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS	0x00000200
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE	0x00000100
+#define BM_DIGCTL_STATUS_LCD_BIST_FAIL	0x00000080
+#define BM_DIGCTL_STATUS_LCD_BIST_PASS	0x00000040
+#define BM_DIGCTL_STATUS_LCD_BIST_DONE	0x00000020
+#define BM_DIGCTL_STATUS_JTAG_IN_USE	0x00000010
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE	1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE	0x0000000E
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)  \
+		(((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE)
+#define BM_DIGCTL_STATUS_WRITTEN	0x00000001
+
+#define HW_DIGCTL_HCLKCOUNT	(0x00000020)
+#define HW_DIGCTL_HCLKCOUNT_SET	(0x00000024)
+#define HW_DIGCTL_HCLKCOUNT_CLR	(0x00000028)
+#define HW_DIGCTL_HCLKCOUNT_TOG	(0x0000002c)
+#define HW_DIGCTL_HCLKCOUNT_ADDR	(REGS_DIGCTL_BASE + 0x00000020)
+
+#define BP_DIGCTL_HCLKCOUNT_COUNT	0
+#define BM_DIGCTL_HCLKCOUNT_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)	(v)
+
+#define HW_DIGCTL_RAMCTRL	(0x00000030)
+#define HW_DIGCTL_RAMCTRL_SET	(0x00000034)
+#define HW_DIGCTL_RAMCTRL_CLR	(0x00000038)
+#define HW_DIGCTL_RAMCTRL_TOG	(0x0000003c)
+#define HW_DIGCTL_RAMCTRL_ADDR	(REGS_DIGCTL_BASE + 0x00000030)
+
+#define BP_DIGCTL_RAMCTRL_RSVD1	12
+#define BM_DIGCTL_RAMCTRL_RSVD1	0xFFFFF000
+#define BF_DIGCTL_RAMCTRL_RSVD1(v) \
+		(((v) << 12) & BM_DIGCTL_RAMCTRL_RSVD1)
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT	8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT	0x00000F00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)  \
+		(((v) << 8) & BM_DIGCTL_RAMCTRL_SPEED_SELECT)
+#define BP_DIGCTL_RAMCTRL_RSVD0	1
+#define BM_DIGCTL_RAMCTRL_RSVD0	0x000000FE
+#define BF_DIGCTL_RAMCTRL_RSVD0(v)  \
+		(((v) << 1) & BM_DIGCTL_RAMCTRL_RSVD0)
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN	0x00000001
+
+#define HW_DIGCTL_RAMREPAIR	(0x00000040)
+#define HW_DIGCTL_RAMREPAIR_SET	(0x00000044)
+#define HW_DIGCTL_RAMREPAIR_CLR	(0x00000048)
+#define HW_DIGCTL_RAMREPAIR_TOG	(0x0000004c)
+#define HW_DIGCTL_RAMREPAIR_ADDR	(REGS_DIGCTL_BASE + 0x00000040)
+
+#define BP_DIGCTL_RAMREPAIR_RSVD1	16
+#define BM_DIGCTL_RAMREPAIR_RSVD1	0xFFFF0000
+#define BF_DIGCTL_RAMREPAIR_RSVD1(v) \
+		(((v) << 16) & BM_DIGCTL_RAMREPAIR_RSVD1)
+#define BP_DIGCTL_RAMREPAIR_ADDR	0
+#define BM_DIGCTL_RAMREPAIR_ADDR	0x0000FFFF
+#define BF_DIGCTL_RAMREPAIR_ADDR(v)  \
+		(((v) << 0) & BM_DIGCTL_RAMREPAIR_ADDR)
+
+#define HW_DIGCTL_ROMCTRL	(0x00000050)
+#define HW_DIGCTL_ROMCTRL_SET	(0x00000054)
+#define HW_DIGCTL_ROMCTRL_CLR	(0x00000058)
+#define HW_DIGCTL_ROMCTRL_TOG	(0x0000005c)
+#define HW_DIGCTL_ROMCTRL_ADDR	(REGS_DIGCTL_BASE + 0x00000050)
+
+#define BP_DIGCTL_ROMCTRL_RSVD0	4
+#define BM_DIGCTL_ROMCTRL_RSVD0	0xFFFFFFF0
+#define BF_DIGCTL_ROMCTRL_RSVD0(v) \
+		(((v) << 4) & BM_DIGCTL_ROMCTRL_RSVD0)
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN	0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN	0x0000000F
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  \
+		(((v) << 0) & BM_DIGCTL_ROMCTRL_RD_MARGIN)
+
+#define HW_DIGCTL_WRITEONCE	(0x00000060)
+#define HW_DIGCTL_WRITEONCE_ADDR	(REGS_DIGCTL_BASE + 0x00000060)
+
+#define BP_DIGCTL_WRITEONCE_BITS	0
+#define BM_DIGCTL_WRITEONCE_BITS	0xFFFFFFFF
+#define BF_DIGCTL_WRITEONCE_BITS(v)	(v)
+
+#define HW_DIGCTL_ENTROPY	(0x00000090)
+#define HW_DIGCTL_ENTROPY_ADDR	(REGS_DIGCTL_BASE + 0x00000090)
+
+#define BP_DIGCTL_ENTROPY_VALUE	0
+#define BM_DIGCTL_ENTROPY_VALUE	0xFFFFFFFF
+#define BF_DIGCTL_ENTROPY_VALUE(v)	(v)
+
+#define HW_DIGCTL_ENTROPY_LATCHED	(0x000000a0)
+#define HW_DIGCTL_ENTROPY_LATCHED_ADDR	(REGS_DIGCTL_BASE + 0x000000a0)
+
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE	0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE	0xFFFFFFFF
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)	(v)
+
+#define HW_DIGCTL_SJTAGDBG	(0x000000b0)
+#define HW_DIGCTL_SJTAGDBG_SET	(0x000000b4)
+#define HW_DIGCTL_SJTAGDBG_CLR	(0x000000b8)
+#define HW_DIGCTL_SJTAGDBG_TOG	(0x000000bc)
+#define HW_DIGCTL_SJTAGDBG_ADDR	(REGS_DIGCTL_BASE + 0x000000b0)
+
+#define BP_DIGCTL_SJTAGDBG_RSVD2	27
+#define BM_DIGCTL_SJTAGDBG_RSVD2	0xF8000000
+#define BF_DIGCTL_SJTAGDBG_RSVD2(v) \
+		(((v) << 27) & BM_DIGCTL_SJTAGDBG_RSVD2)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE	16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE	0x07FF0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)  \
+		(((v) << 16) & BM_DIGCTL_SJTAGDBG_SJTAG_STATE)
+#define BP_DIGCTL_SJTAGDBG_RSVD1	11
+#define BM_DIGCTL_SJTAGDBG_RSVD1	0x0000F800
+#define BF_DIGCTL_SJTAGDBG_RSVD1(v)  \
+		(((v) << 11) & BM_DIGCTL_SJTAGDBG_RSVD1)
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO	0x00000400
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI	0x00000200
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE	0x00000100
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE	4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE	0x000000F0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)  \
+		(((v) << 4) & BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE)
+#define BM_DIGCTL_SJTAGDBG_ACTIVE	0x00000008
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE	0x00000004
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA	0x00000002
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE	0x00000001
+
+#define HW_DIGCTL_MICROSECONDS	(0x000000c0)
+#define HW_DIGCTL_MICROSECONDS_SET	(0x000000c4)
+#define HW_DIGCTL_MICROSECONDS_CLR	(0x000000c8)
+#define HW_DIGCTL_MICROSECONDS_TOG	(0x000000cc)
+#define HW_DIGCTL_MICROSECONDS_ADDR	(REGS_DIGCTL_BASE + 0x000000c0)
+
+#define BP_DIGCTL_MICROSECONDS_VALUE	0
+#define BM_DIGCTL_MICROSECONDS_VALUE	0xFFFFFFFF
+#define BF_DIGCTL_MICROSECONDS_VALUE(v)	(v)
+
+#define HW_DIGCTL_DBGRD	(0x000000d0)
+#define HW_DIGCTL_DBGRD_ADDR	(REGS_DIGCTL_BASE + 0x000000d0)
+
+#define BP_DIGCTL_DBGRD_COMPLEMENT	0
+#define BM_DIGCTL_DBGRD_COMPLEMENT	0xFFFFFFFF
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)	(v)
+
+#define HW_DIGCTL_DBG	(0x000000e0)
+#define HW_DIGCTL_DBG_ADDR	(REGS_DIGCTL_BASE + 0x000000e0)
+
+#define BP_DIGCTL_DBG_VALUE	0
+#define BM_DIGCTL_DBG_VALUE	0xFFFFFFFF
+#define BF_DIGCTL_DBG_VALUE(v)	(v)
+
+#define HW_DIGCTL_OCRAM_BIST_CSR	(0x000000f0)
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET	(0x000000f4)
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR	(0x000000f8)
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG	(0x000000fc)
+#define HW_DIGCTL_OCRAM_BIST_CSR_ADDR	(REGS_DIGCTL_BASE + 0x000000f0)
+
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1	11
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1	0xFFFFF800
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) \
+		(((v) << 11) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD1)
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE	0x00000400
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE	0x00000200
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN	0x00000100
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0	4
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0	0x000000F0
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v)  \
+		(((v) << 4) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD0)
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL	0x00000008
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS	0x00000004
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE	0x00000002
+#define BM_DIGCTL_OCRAM_BIST_CSR_START	0x00000001
+
+#define HW_DIGCTL_OCRAM_STATUS0	(0x00000110)
+#define HW_DIGCTL_OCRAM_STATUS0_SET	(0x00000114)
+#define HW_DIGCTL_OCRAM_STATUS0_CLR	(0x00000118)
+#define HW_DIGCTL_OCRAM_STATUS0_TOG	(0x0000011c)
+#define HW_DIGCTL_OCRAM_STATUS0_ADDR	(REGS_DIGCTL_BASE + 0x00000110)
+
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00	0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS1	(0x00000120)
+#define HW_DIGCTL_OCRAM_STATUS1_SET	(0x00000124)
+#define HW_DIGCTL_OCRAM_STATUS1_CLR	(0x00000128)
+#define HW_DIGCTL_OCRAM_STATUS1_TOG	(0x0000012c)
+#define HW_DIGCTL_OCRAM_STATUS1_ADDR	(REGS_DIGCTL_BASE + 0x00000120)
+
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01	0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS2	(0x00000130)
+#define HW_DIGCTL_OCRAM_STATUS2_SET	(0x00000134)
+#define HW_DIGCTL_OCRAM_STATUS2_CLR	(0x00000138)
+#define HW_DIGCTL_OCRAM_STATUS2_TOG	(0x0000013c)
+#define HW_DIGCTL_OCRAM_STATUS2_ADDR	(REGS_DIGCTL_BASE + 0x00000130)
+
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10	0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS3	(0x00000140)
+#define HW_DIGCTL_OCRAM_STATUS3_SET	(0x00000144)
+#define HW_DIGCTL_OCRAM_STATUS3_CLR	(0x00000148)
+#define HW_DIGCTL_OCRAM_STATUS3_TOG	(0x0000014c)
+#define HW_DIGCTL_OCRAM_STATUS3_ADDR	(REGS_DIGCTL_BASE + 0x00000140)
+
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11	0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS4	(0x00000150)
+#define HW_DIGCTL_OCRAM_STATUS4_SET	(0x00000154)
+#define HW_DIGCTL_OCRAM_STATUS4_CLR	(0x00000158)
+#define HW_DIGCTL_OCRAM_STATUS4_TOG	(0x0000015c)
+#define HW_DIGCTL_OCRAM_STATUS4_ADDR	(REGS_DIGCTL_BASE + 0x00000150)
+
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20	0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS5	(0x00000160)
+#define HW_DIGCTL_OCRAM_STATUS5_SET	(0x00000164)
+#define HW_DIGCTL_OCRAM_STATUS5_CLR	(0x00000168)
+#define HW_DIGCTL_OCRAM_STATUS5_TOG	(0x0000016c)
+#define HW_DIGCTL_OCRAM_STATUS5_ADDR	(REGS_DIGCTL_BASE + 0x00000160)
+
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21	0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS6	(0x00000170)
+#define HW_DIGCTL_OCRAM_STATUS6_SET	(0x00000174)
+#define HW_DIGCTL_OCRAM_STATUS6_CLR	(0x00000178)
+#define HW_DIGCTL_OCRAM_STATUS6_TOG	(0x0000017c)
+#define HW_DIGCTL_OCRAM_STATUS6_ADDR	(REGS_DIGCTL_BASE + 0x00000170)
+
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30	0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS7	(0x00000180)
+#define HW_DIGCTL_OCRAM_STATUS7_SET	(0x00000184)
+#define HW_DIGCTL_OCRAM_STATUS7_CLR	(0x00000188)
+#define HW_DIGCTL_OCRAM_STATUS7_TOG	(0x0000018c)
+#define HW_DIGCTL_OCRAM_STATUS7_ADDR	(REGS_DIGCTL_BASE + 0x00000180)
+
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31	0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31	0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)	(v)
+
+#define HW_DIGCTL_OCRAM_STATUS8	(0x00000190)
+#define HW_DIGCTL_OCRAM_STATUS8_SET	(0x00000194)
+#define HW_DIGCTL_OCRAM_STATUS8_CLR	(0x00000198)
+#define HW_DIGCTL_OCRAM_STATUS8_TOG	(0x0000019c)
+#define HW_DIGCTL_OCRAM_STATUS8_ADDR	(REGS_DIGCTL_BASE + 0x00000190)
+
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD3	29
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD3	0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) \
+		(((v) << 29) & BM_DIGCTL_OCRAM_STATUS8_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01	16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01	0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01)
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD2	13
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD2	0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v)  \
+		(((v) << 13) & BM_DIGCTL_OCRAM_STATUS8_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00	0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00	0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00)
+
+#define HW_DIGCTL_OCRAM_STATUS9	(0x000001a0)
+#define HW_DIGCTL_OCRAM_STATUS9_SET	(0x000001a4)
+#define HW_DIGCTL_OCRAM_STATUS9_CLR	(0x000001a8)
+#define HW_DIGCTL_OCRAM_STATUS9_TOG	(0x000001ac)
+#define HW_DIGCTL_OCRAM_STATUS9_ADDR	(REGS_DIGCTL_BASE + 0x000001a0)
+
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD3	29
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD3	0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) \
+		(((v) << 29) & BM_DIGCTL_OCRAM_STATUS9_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11	16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11	0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11)
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD2	13
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD2	0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v)  \
+		(((v) << 13) & BM_DIGCTL_OCRAM_STATUS9_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10	0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10	0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10)
+
+#define HW_DIGCTL_OCRAM_STATUS10	(0x000001b0)
+#define HW_DIGCTL_OCRAM_STATUS10_SET	(0x000001b4)
+#define HW_DIGCTL_OCRAM_STATUS10_CLR	(0x000001b8)
+#define HW_DIGCTL_OCRAM_STATUS10_TOG	(0x000001bc)
+#define HW_DIGCTL_OCRAM_STATUS10_ADDR	(REGS_DIGCTL_BASE + 0x000001b0)
+
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD3	29
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD3	0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) \
+		(((v) << 29) & BM_DIGCTL_OCRAM_STATUS10_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21	16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21	0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21)
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD2	13
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD2	0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v)  \
+		(((v) << 13) & BM_DIGCTL_OCRAM_STATUS10_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20	0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20	0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20)
+
+#define HW_DIGCTL_OCRAM_STATUS11	(0x000001c0)
+#define HW_DIGCTL_OCRAM_STATUS11_SET	(0x000001c4)
+#define HW_DIGCTL_OCRAM_STATUS11_CLR	(0x000001c8)
+#define HW_DIGCTL_OCRAM_STATUS11_TOG	(0x000001cc)
+#define HW_DIGCTL_OCRAM_STATUS11_ADDR	(REGS_DIGCTL_BASE + 0x000001c0)
+
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD3	29
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD3	0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) \
+		(((v) << 29) & BM_DIGCTL_OCRAM_STATUS11_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31	16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31	0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31)
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD2	13
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD2	0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v)  \
+		(((v) << 13) & BM_DIGCTL_OCRAM_STATUS11_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30	0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30	0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30)
+
+#define HW_DIGCTL_OCRAM_STATUS12	(0x000001d0)
+#define HW_DIGCTL_OCRAM_STATUS12_SET	(0x000001d4)
+#define HW_DIGCTL_OCRAM_STATUS12_CLR	(0x000001d8)
+#define HW_DIGCTL_OCRAM_STATUS12_TOG	(0x000001dc)
+#define HW_DIGCTL_OCRAM_STATUS12_ADDR	(REGS_DIGCTL_BASE + 0x000001d0)
+
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD3	28
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD3	0xF0000000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) \
+		(((v) << 28) & BM_DIGCTL_OCRAM_STATUS12_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11	24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11	0x0F000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v)  \
+		(((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD2	20
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD2	0x00F00000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v)  \
+		(((v) << 20) & BM_DIGCTL_OCRAM_STATUS12_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10	16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10	0x000F0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD1	12
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD1	0x0000F000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v)  \
+		(((v) << 12) & BM_DIGCTL_OCRAM_STATUS12_RSVD1)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01	8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01	0x00000F00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v)  \
+		(((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD0	4
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD0	0x000000F0
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v)  \
+		(((v) << 4) & BM_DIGCTL_OCRAM_STATUS12_RSVD0)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00	0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00	0x0000000F
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00)
+
+#define HW_DIGCTL_OCRAM_STATUS13	(0x000001e0)
+#define HW_DIGCTL_OCRAM_STATUS13_SET	(0x000001e4)
+#define HW_DIGCTL_OCRAM_STATUS13_CLR	(0x000001e8)
+#define HW_DIGCTL_OCRAM_STATUS13_TOG	(0x000001ec)
+#define HW_DIGCTL_OCRAM_STATUS13_ADDR	(REGS_DIGCTL_BASE + 0x000001e0)
+
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD3	28
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD3	0xF0000000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) \
+		(((v) << 28) & BM_DIGCTL_OCRAM_STATUS13_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31	24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31	0x0F000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v)  \
+		(((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD2	20
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD2	0x00F00000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v)  \
+		(((v) << 20) & BM_DIGCTL_OCRAM_STATUS13_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30	16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30	0x000F0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v)  \
+		(((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD1	12
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD1	0x0000F000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v)  \
+		(((v) << 12) & BM_DIGCTL_OCRAM_STATUS13_RSVD1)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21	8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21	0x00000F00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v)  \
+		(((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD0	4
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD0	0x000000F0
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v)  \
+		(((v) << 4) & BM_DIGCTL_OCRAM_STATUS13_RSVD0)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20	0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20	0x0000000F
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v)  \
+		(((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20)
+
+#define HW_DIGCTL_SCRATCH0	(0x00000290)
+#define HW_DIGCTL_SCRATCH0_ADDR	(REGS_DIGCTL_BASE + 0x00000290)
+
+#define BP_DIGCTL_SCRATCH0_PTR	0
+#define BM_DIGCTL_SCRATCH0_PTR	0xFFFFFFFF
+#define BF_DIGCTL_SCRATCH0_PTR(v)	(v)
+
+#define HW_DIGCTL_SCRATCH1	(0x000002a0)
+#define HW_DIGCTL_SCRATCH1_ADDR	(REGS_DIGCTL_BASE + 0x000002a0)
+
+#define BP_DIGCTL_SCRATCH1_PTR	0
+#define BM_DIGCTL_SCRATCH1_PTR	0xFFFFFFFF
+#define BF_DIGCTL_SCRATCH1_PTR(v)	(v)
+
+#define HW_DIGCTL_ARMCACHE	(0x000002b0)
+#define HW_DIGCTL_ARMCACHE_ADDR	(REGS_DIGCTL_BASE + 0x000002b0)
+
+#define BP_DIGCTL_ARMCACHE_RSVD4	18
+#define BM_DIGCTL_ARMCACHE_RSVD4	0xFFFC0000
+#define BF_DIGCTL_ARMCACHE_RSVD4(v) \
+		(((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4)
 #define BP_DIGCTL_ARMCACHE_VALID_SS	16
+#define BM_DIGCTL_ARMCACHE_VALID_SS	0x00030000
+#define BF_DIGCTL_ARMCACHE_VALID_SS(v)  \
+		(((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD3	14
+#define BM_DIGCTL_ARMCACHE_RSVD3	0x0000C000
+#define BF_DIGCTL_ARMCACHE_RSVD3(v)  \
+		(((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3)
+#define BP_DIGCTL_ARMCACHE_DRTY_SS	12
+#define BM_DIGCTL_ARMCACHE_DRTY_SS	0x00003000
+#define BF_DIGCTL_ARMCACHE_DRTY_SS(v)  \
+		(((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD2	10
+#define BM_DIGCTL_ARMCACHE_RSVD2	0x00000C00
+#define BF_DIGCTL_ARMCACHE_RSVD2(v)  \
+		(((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2)
+#define BP_DIGCTL_ARMCACHE_CACHE_SS	8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS	0x00000300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  \
+		(((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD1	6
+#define BM_DIGCTL_ARMCACHE_RSVD1	0x000000C0
+#define BF_DIGCTL_ARMCACHE_RSVD1(v)  \
+		(((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS	4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS	0x00000030
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)  \
+		(((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD0	2
+#define BM_DIGCTL_ARMCACHE_RSVD0	0x0000000C
+#define BF_DIGCTL_ARMCACHE_RSVD0(v)  \
+		(((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS	0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS	0x00000003
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)  \
+		(((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS)
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW	(0x000002c0)
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR	(REGS_DIGCTL_BASE + 0x000002c0)
+
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR	0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR	0xFFFFFFFF
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)	(v)
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH	(0x000002d0)
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR	(REGS_DIGCTL_BASE + 0x000002d0)
+
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR	0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR	0xFFFFFFFF
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)	(v)
+
+#define HW_DIGCTL_SGTL	(0x00000300)
+#define HW_DIGCTL_SGTL_ADDR	(REGS_DIGCTL_BASE + 0x00000300)
+
+#define BP_DIGCTL_SGTL_COPYRIGHT	0
+#define BM_DIGCTL_SGTL_COPYRIGHT	0xFFFFFFFF
+#define BF_DIGCTL_SGTL_COPYRIGHT(v)	(v)
+
+#define HW_DIGCTL_CHIPID	(0x00000310)
+#define HW_DIGCTL_CHIPID_ADDR	(REGS_DIGCTL_BASE + 0x00000310)
+
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE	16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE	0xFFFF0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \
+		(((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE)
+#define BP_DIGCTL_CHIPID_RSVD0	8
+#define BM_DIGCTL_CHIPID_RSVD0	0x0000FF00
+#define BF_DIGCTL_CHIPID_RSVD0(v)  \
+		(((v) << 8) & BM_DIGCTL_CHIPID_RSVD0)
+#define BP_DIGCTL_CHIPID_REVISION	0
+#define BM_DIGCTL_CHIPID_REVISION	0x000000FF
+#define BF_DIGCTL_CHIPID_REVISION(v)  \
+		(((v) << 0) & BM_DIGCTL_CHIPID_REVISION)
+
+#define HW_DIGCTL_AHB_STATS_SELECT	(0x00000330)
+#define HW_DIGCTL_AHB_STATS_SELECT_ADDR	(REGS_DIGCTL_BASE + 0x00000330)
+
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3	28
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3	0xF0000000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) \
+		(((v) << 28) & BM_DIGCTL_AHB_STATS_SELECT_RSVD3)
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT	24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT	0x0F000000
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)  \
+		(((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB  0x4
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2	20
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2	0x00F00000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v)  \
+		(((v) << 20) & BM_DIGCTL_AHB_STATS_SELECT_RSVD2)
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT	16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT	0x000F0000
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)  \
+		(((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1	12
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1	0x0000F000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v)  \
+		(((v) << 12) & BM_DIGCTL_AHB_STATS_SELECT_RSVD1)
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT	8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT	0x00000F00
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)  \
+		(((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0	4
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0	0x000000F0
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v)  \
+		(((v) << 4) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0)
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT	0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT	0x0000000F
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)  \
+		(((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES	(0x00000340)
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x00000340)
+
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT	0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L0_AHB_DATA_STALLED	(0x00000350)
+#define HW_DIGCTL_L0_AHB_DATA_STALLED_ADDR	(REGS_DIGCTL_BASE + 0x00000350)
+
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT	0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)	(v)
+
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES	(0x00000360)
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x00000360)
+
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT	0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES	(0x00000370)
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x00000370)
+
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT	0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L1_AHB_DATA_STALLED	(0x00000380)
+#define HW_DIGCTL_L1_AHB_DATA_STALLED_ADDR	(REGS_DIGCTL_BASE + 0x00000380)
+
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT	0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)	(v)
+
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES	(0x00000390)
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x00000390)
+
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT	0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES	(0x000003a0)
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x000003a0)
+
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT	0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L2_AHB_DATA_STALLED	(0x000003b0)
+#define HW_DIGCTL_L2_AHB_DATA_STALLED_ADDR	(REGS_DIGCTL_BASE + 0x000003b0)
+
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT	0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)	(v)
+
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES	(0x000003c0)
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x000003c0)
+
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT	0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES	(0x000003d0)
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x000003d0)
+
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT	0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v)	(v)
+
+#define HW_DIGCTL_L3_AHB_DATA_STALLED	(0x000003e0)
+#define HW_DIGCTL_L3_AHB_DATA_STALLED_ADDR	(REGS_DIGCTL_BASE + 0x000003e0)
+
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT	0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)	(v)
+
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES	(0x000003f0)
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES_ADDR	(REGS_DIGCTL_BASE + 0x000003f0)
+
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT	0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT	0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)	(v)
+
+/*
+ *  multi-register-define name HW_DIGCTL_MPTEn_LOC
+ *              base 0x00000400
+ *              count 16
+ *              offset 0x10
+ */
+
+#define HW_DIGCTL_MPTEn_LOCn	0x00000400
+#define HW_DIGCTL_MPTEn_LOCn_SET	0x00000404
+#define HW_DIGCTL_MPTEn_LOCn_CLR	0x00000408
+#define HW_DIGCTL_MPTEn_LOCn_TOG	0x0000040c
+#define HW_DIGCTL_MPTEn_LOCn_MULTIOFFSET	hwreg.multi_offset
+
+#define BP_DIGCTL_MPTEn_LOC_RSVD0	12
+#define BM_DIGCTL_MPTEn_LOC_RSVD0	0xFFFFF000
+#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) \
+		(((v) << 12) & BM_DIGCTL_MPTEn_LOC_RSVD0)
+#define BP_DIGCTL_MPTEn_LOC_LOC	0
+#define BM_DIGCTL_MPTEn_LOC_LOC	0x00000FFF
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)  \
+		(((v) << 0) & BM_DIGCTL_MPTEn_LOC_LOC)
+
+#define HW_DIGCTL_EMICLK_DELAY	(0x00000500)
+#define HW_DIGCTL_EMICLK_DELAY_ADDR	(REGS_DIGCTL_BASE + 0x00000500)
+
+#define BP_DIGCTL_EMICLK_DELAY_RSVD0	5
+#define BM_DIGCTL_EMICLK_DELAY_RSVD0	0xFFFFFFE0
+#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) \
+		(((v) << 5) & BM_DIGCTL_EMICLK_DELAY_RSVD0)
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS	0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS	0x0000001F
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  \
+		(((v) << 0) & BM_DIGCTL_EMICLK_DELAY_NUM_TAPS)
+#endif /* __ARCH_ARM___DIGCTL_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
index 98773fc33d7b..59029c052e62 100644
--- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
@@ -1,7 +1,7 @@
 /*
- * stmp378x: EMI register definitions
+ * STMP EMI Register Definitions
  *
- * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,9 +17,229 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
  */
-#define REGS_EMI_BASE	(STMP3XXX_REGS_BASE + 0x20000)
-#define REGS_EMI_PHYS	0x80020000
-#define REGS_EMI_SIZE	0x2000
 
-#define HW_EMI_STAT		0x10
+#ifndef __ARCH_ARM___EMI_H
+#define __ARCH_ARM___EMI_H  1
+
+#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
+#define REGS_EMI_PHYS (0x80020000)
+#define REGS_EMI_SIZE 0x00002000
+
+#define HW_EMI_CTRL	(0x00000000)
+#define HW_EMI_CTRL_SET	(0x00000004)
+#define HW_EMI_CTRL_CLR	(0x00000008)
+#define HW_EMI_CTRL_TOG	(0x0000000c)
+#define HW_EMI_CTRL_ADDR	(REGS_EMI_BASE + 0x00000000)
+
+#define BM_EMI_CTRL_SFTRST	0x80000000
+#define BM_EMI_CTRL_CLKGATE	0x40000000
+#define BM_EMI_CTRL_TRAP_SR	0x20000000
+#define BM_EMI_CTRL_TRAP_INIT	0x10000000
+#define BP_EMI_CTRL_AXI_DEPTH	26
+#define BM_EMI_CTRL_AXI_DEPTH	0x0C000000
+#define BF_EMI_CTRL_AXI_DEPTH(v)  \
+		(((v) << 26) & BM_EMI_CTRL_AXI_DEPTH)
+#define BV_EMI_CTRL_AXI_DEPTH__ONE   0x0
+#define BV_EMI_CTRL_AXI_DEPTH__TWO   0x1
+#define BV_EMI_CTRL_AXI_DEPTH__THREE 0x2
+#define BV_EMI_CTRL_AXI_DEPTH__FOUR  0x3
+#define BM_EMI_CTRL_DLL_SHIFT_RESET	0x02000000
+#define BM_EMI_CTRL_DLL_RESET	0x01000000
+#define BP_EMI_CTRL_ARB_MODE	22
+#define BM_EMI_CTRL_ARB_MODE	0x00C00000
+#define BF_EMI_CTRL_ARB_MODE(v)  \
+		(((v) << 22) & BM_EMI_CTRL_ARB_MODE)
+#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP     0x0
+#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID  0x1
+#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY 0x2
+#define BM_EMI_CTRL_RSVD3	0x00200000
+#define BP_EMI_CTRL_PORT_PRIORITY_ORDER	16
+#define BM_EMI_CTRL_PORT_PRIORITY_ORDER	0x001F0000
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v)  \
+		(((v) << 16) & BM_EMI_CTRL_PORT_PRIORITY_ORDER)
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123 0x00
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312 0x01
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231 0x02
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321 0x03
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213 0x04
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132 0x05
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023 0x06
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302 0x07
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230 0x08
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320 0x09
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203 0x0A
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032 0x0B
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013 0x0C
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301 0x0D
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130 0x0E
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310 0x0F
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103 0x10
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031 0x11
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012 0x12
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201 0x13
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120 0x14
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210 0x15
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102 0x16
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021 0x17
+#define BM_EMI_CTRL_RSVD2	0x00008000
+#define BP_EMI_CTRL_PRIORITY_WRITE_ITER	12
+#define BM_EMI_CTRL_PRIORITY_WRITE_ITER	0x00007000
+#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v)  \
+		(((v) << 12) & BM_EMI_CTRL_PRIORITY_WRITE_ITER)
+#define BM_EMI_CTRL_RSVD1	0x00000800
+#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE	8
+#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE	0x00000700
+#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v)  \
+		(((v) << 8) & BM_EMI_CTRL_HIGH_PRIORITY_WRITE)
+#define BM_EMI_CTRL_RSVD0	0x00000080
+#define BM_EMI_CTRL_MEM_WIDTH	0x00000040
+#define BM_EMI_CTRL_WRITE_PROTECT	0x00000020
+#define BM_EMI_CTRL_RESET_OUT	0x00000010
+#define BP_EMI_CTRL_CE_SELECT	0
+#define BM_EMI_CTRL_CE_SELECT	0x0000000F
+#define BF_EMI_CTRL_CE_SELECT(v)  \
+		(((v) << 0) & BM_EMI_CTRL_CE_SELECT)
+#define BV_EMI_CTRL_CE_SELECT__NONE 0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0  0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1  0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2  0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3  0x8
+
+#define HW_EMI_STAT	(0x00000010)
+#define HW_EMI_STAT_ADDR	(REGS_EMI_BASE + 0x00000010)
+
+#define BM_EMI_STAT_DRAM_PRESENT	0x80000000
+#define BM_EMI_STAT_NOR_PRESENT	0x40000000
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED	0x20000000
+#define BP_EMI_STAT_RSVD0	2
+#define BM_EMI_STAT_RSVD0	0x1FFFFFFC
+#define BF_EMI_STAT_RSVD0(v)  \
+		(((v) << 2) & BM_EMI_STAT_RSVD0)
+#define BM_EMI_STAT_DRAM_HALTED	0x00000002
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED     0x1
+#define BM_EMI_STAT_NOR_BUSY	0x00000001
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY     0x1
+
+#define HW_EMI_TIME	(0x00000020)
+#define HW_EMI_TIME_SET	(0x00000024)
+#define HW_EMI_TIME_CLR	(0x00000028)
+#define HW_EMI_TIME_TOG	(0x0000002c)
+#define HW_EMI_TIME_ADDR	(REGS_EMI_BASE + 0x00000020)
+
+#define BP_EMI_TIME_RSVD4	28
+#define BM_EMI_TIME_RSVD4	0xF0000000
+#define BF_EMI_TIME_RSVD4(v) \
+		(((v) << 28) & BM_EMI_TIME_RSVD4)
+#define BP_EMI_TIME_THZ	24
+#define BM_EMI_TIME_THZ	0x0F000000
+#define BF_EMI_TIME_THZ(v)  \
+		(((v) << 24) & BM_EMI_TIME_THZ)
+#define BP_EMI_TIME_RSVD2	20
+#define BM_EMI_TIME_RSVD2	0x00F00000
+#define BF_EMI_TIME_RSVD2(v)  \
+		(((v) << 20) & BM_EMI_TIME_RSVD2)
+#define BP_EMI_TIME_TDH	16
+#define BM_EMI_TIME_TDH	0x000F0000
+#define BF_EMI_TIME_TDH(v)  \
+		(((v) << 16) & BM_EMI_TIME_TDH)
+#define BP_EMI_TIME_RSVD1	13
+#define BM_EMI_TIME_RSVD1	0x0000E000
+#define BF_EMI_TIME_RSVD1(v)  \
+		(((v) << 13) & BM_EMI_TIME_RSVD1)
+#define BP_EMI_TIME_TDS	8
+#define BM_EMI_TIME_TDS	0x00001F00
+#define BF_EMI_TIME_TDS(v)  \
+		(((v) << 8) & BM_EMI_TIME_TDS)
+#define BP_EMI_TIME_RSVD0	4
+#define BM_EMI_TIME_RSVD0	0x000000F0
+#define BF_EMI_TIME_RSVD0(v)  \
+		(((v) << 4) & BM_EMI_TIME_RSVD0)
+#define BP_EMI_TIME_TAS	0
+#define BM_EMI_TIME_TAS	0x0000000F
+#define BF_EMI_TIME_TAS(v)  \
+		(((v) << 0) & BM_EMI_TIME_TAS)
+
+#define HW_EMI_DDR_TEST_MODE_CSR	(0x00000030)
+#define HW_EMI_DDR_TEST_MODE_CSR_SET	(0x00000034)
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR	(0x00000038)
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG	(0x0000003c)
+#define HW_EMI_DDR_TEST_MODE_CSR_ADDR	(REGS_EMI_BASE + 0x00000030)
+
+#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1	2
+#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1	0xFFFFFFFC
+#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v) \
+		(((v) << 2) & BM_EMI_DDR_TEST_MODE_CSR_RSVD1)
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE	0x00000002
+#define BM_EMI_DDR_TEST_MODE_CSR_START	0x00000001
+
+#define HW_EMI_DEBUG	(0x00000080)
+#define HW_EMI_DEBUG_ADDR	(REGS_EMI_BASE + 0x00000080)
+
+#define BP_EMI_DEBUG_RSVD1	4
+#define BM_EMI_DEBUG_RSVD1	0xFFFFFFF0
+#define BF_EMI_DEBUG_RSVD1(v) \
+		(((v) << 4) & BM_EMI_DEBUG_RSVD1)
+#define BP_EMI_DEBUG_NOR_STATE	0
+#define BM_EMI_DEBUG_NOR_STATE	0x0000000F
+#define BF_EMI_DEBUG_NOR_STATE(v)  \
+		(((v) << 0) & BM_EMI_DEBUG_NOR_STATE)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS0	(0x00000090)
+#define HW_EMI_DDR_TEST_MODE_STATUS0_ADDR	(REGS_EMI_BASE + 0x00000090)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1	13
+#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1	0xFFFFE000
+#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v) \
+		(((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1)
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0	0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0	0x00001FFF
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)  \
+		(((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS1	(0x000000a0)
+#define HW_EMI_DDR_TEST_MODE_STATUS1_ADDR	(REGS_EMI_BASE + 0x000000a0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1	13
+#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1	0xFFFFE000
+#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v) \
+		(((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1)
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1	0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1	0x00001FFF
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)  \
+		(((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS2	(0x000000b0)
+#define HW_EMI_DDR_TEST_MODE_STATUS2_ADDR	(REGS_EMI_BASE + 0x000000b0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0	0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0	0xFFFFFFFF
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)	(v)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS3	(0x000000c0)
+#define HW_EMI_DDR_TEST_MODE_STATUS3_ADDR	(REGS_EMI_BASE + 0x000000c0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1	0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1	0xFFFFFFFF
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)	(v)
+
+#define HW_EMI_VERSION	(0x000000f0)
+#define HW_EMI_VERSION_ADDR	(REGS_EMI_BASE + 0x000000f0)
+
+#define BP_EMI_VERSION_MAJOR	24
+#define BM_EMI_VERSION_MAJOR	0xFF000000
+#define BF_EMI_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_EMI_VERSION_MAJOR)
+#define BP_EMI_VERSION_MINOR	16
+#define BM_EMI_VERSION_MINOR	0x00FF0000
+#define BF_EMI_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_EMI_VERSION_MINOR)
+#define BP_EMI_VERSION_STEP	0
+#define BM_EMI_VERSION_STEP	0x0000FFFF
+#define BF_EMI_VERSION_STEP(v)  \
+		(((v) << 0) & BM_EMI_VERSION_STEP)
+#endif /* __ARCH_ARM___EMI_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
index e3438ecb6eab..7438f17cbca5 100644
--- a/arch/arm/mach-stmp378x/include/mach/regs-power.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h
@@ -1,7 +1,7 @@
 /*
- * stmp378x: POWER register definitions
+ * STMP POWER Register Definitions
  *
- * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,280 +17,562 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
  */
-#ifndef _MACH_REGS_POWER
-#define _MACH_REGS_POWER
-
-#define REGS_POWER_BASE	(STMP3XXX_REGS_BASE + 0x44000)
-#define REGS_POWER_PHYS	0x80044000
-#define REGS_POWER_SIZE	0x2000
-
-#define HW_POWER_CTRL		0x0
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO	0x00000001
-#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO	0
-#define BM_POWER_CTRL_ENIRQ_PSWITCH	0x00020000
-#define BM_POWER_CTRL_PSWITCH_IRQ	0x00100000
-#define BM_POWER_CTRL_CLKGATE	0x40000000
-
-#define HW_POWER_5VCTRL		0x10
-#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT	0x00000040
 
-#define HW_POWER_LOOPCTRL	0xb0
+#ifndef __ARCH_ARM___POWER_H
+#define __ARCH_ARM___POWER_H  1
 
-#define HW_POWER_MINPWR		0x20
+#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
+#define REGS_POWER_PHYS (0x80044000)
+#define REGS_POWER_SIZE 0x00002000
 
-#define HW_POWER_CHARGE		0x30
+#define HW_POWER_CTRL	(0x00000000)
+#define HW_POWER_CTRL_SET	(0x00000004)
+#define HW_POWER_CTRL_CLR	(0x00000008)
+#define HW_POWER_CTRL_TOG	(0x0000000c)
+#define HW_POWER_CTRL_ADDR	(REGS_POWER_BASE + 0x00000000)
 
-#define HW_POWER_VDDDCTRL	0x40
-
-#define HW_POWER_VDDACTRL	0x50
+#define BM_POWER_CTRL_RSRVD3	0x80000000
+#define BM_POWER_CTRL_CLKGATE	0x40000000
+#define BP_POWER_CTRL_RSRVD2	28
+#define BM_POWER_CTRL_RSRVD2	0x30000000
+#define BF_POWER_CTRL_RSRVD2(v)  \
+		(((v) << 28) & BM_POWER_CTRL_RSRVD2)
+#define BM_POWER_CTRL_PSWITCH_MID_TRAN	0x08000000
+#define BP_POWER_CTRL_RSRVD1	25
+#define BM_POWER_CTRL_RSRVD1	0x06000000
+#define BF_POWER_CTRL_RSRVD1(v)  \
+		(((v) << 25) & BM_POWER_CTRL_RSRVD1)
+#define BM_POWER_CTRL_DCDC4P2_BO_IRQ	0x01000000
+#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO	0x00800000
+#define BM_POWER_CTRL_VDD5V_DROOP_IRQ	0x00400000
+#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP	0x00200000
+#define BM_POWER_CTRL_PSWITCH_IRQ	0x00100000
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC	0x00080000
+#define BM_POWER_CTRL_POLARITY_PSWITCH	0x00040000
+#define BM_POWER_CTRL_ENIRQ_PSWITCH	0x00020000
+#define BM_POWER_CTRL_POLARITY_DC_OK	0x00010000
+#define BM_POWER_CTRL_DC_OK_IRQ	0x00008000
+#define BM_POWER_CTRL_ENIRQ_DC_OK	0x00004000
+#define BM_POWER_CTRL_BATT_BO_IRQ	0x00002000
+#define BM_POWER_CTRL_ENIRQBATT_BO	0x00001000
+#define BM_POWER_CTRL_VDDIO_BO_IRQ	0x00000800
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO	0x00000400
+#define BM_POWER_CTRL_VDDA_BO_IRQ	0x00000200
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO	0x00000100
+#define BM_POWER_CTRL_VDDD_BO_IRQ	0x00000080
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO	0x00000040
+#define BM_POWER_CTRL_POLARITY_VBUSVALID	0x00000020
+#define BM_POWER_CTRL_VBUSVALID_IRQ	0x00000010
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID	0x00000008
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO	0x00000004
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ	0x00000002
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO	0x00000001
 
-#define HW_POWER_VDDIOCTRL	0x60
-#define BM_POWER_VDDIOCTRL_TRG	0x0000001F
+#define HW_POWER_5VCTRL	(0x00000010)
+#define HW_POWER_5VCTRL_SET	(0x00000014)
+#define HW_POWER_5VCTRL_CLR	(0x00000018)
+#define HW_POWER_5VCTRL_TOG	(0x0000001c)
+#define HW_POWER_5VCTRL_ADDR	(REGS_POWER_BASE + 0x00000010)
+
+#define BP_POWER_5VCTRL_RSRVD6	30
+#define BM_POWER_5VCTRL_RSRVD6	0xC0000000
+#define BF_POWER_5VCTRL_RSRVD6(v) \
+		(((v) << 30) & BM_POWER_5VCTRL_RSRVD6)
+#define BP_POWER_5VCTRL_VBUSDROOP_TRSH	28
+#define BM_POWER_5VCTRL_VBUSDROOP_TRSH	0x30000000
+#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v)  \
+		(((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH)
+#define BM_POWER_5VCTRL_RSRVD5	0x08000000
+#define BP_POWER_5VCTRL_HEADROOM_ADJ	24
+#define BM_POWER_5VCTRL_HEADROOM_ADJ	0x07000000
+#define BF_POWER_5VCTRL_HEADROOM_ADJ(v)  \
+		(((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ)
+#define BP_POWER_5VCTRL_RSRVD4	21
+#define BM_POWER_5VCTRL_RSRVD4	0x00E00000
+#define BF_POWER_5VCTRL_RSRVD4(v)  \
+		(((v) << 21) & BM_POWER_5VCTRL_RSRVD4)
+#define BM_POWER_5VCTRL_PWD_CHARGE_4P2	0x00100000
+#define BP_POWER_5VCTRL_RSRVD3	18
+#define BM_POWER_5VCTRL_RSRVD3	0x000C0000
+#define BF_POWER_5VCTRL_RSRVD3(v)  \
+		(((v) << 18) & BM_POWER_5VCTRL_RSRVD3)
+#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT	12
+#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT	0x0003F000
+#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)  \
+		(((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
+#define BM_POWER_5VCTRL_RSRVD2	0x00000800
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH	8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH	0x00000700
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)  \
+		(((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH)
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT	0x00000080
+#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT	0x00000040
+#define BM_POWER_5VCTRL_DCDC_XFER	0x00000020
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT	0x00000010
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B	0x00000008
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO	0x00000004
+#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS	0x00000002
+#define BM_POWER_5VCTRL_ENABLE_DCDC	0x00000001
+
+#define HW_POWER_MINPWR	(0x00000020)
+#define HW_POWER_MINPWR_SET	(0x00000024)
+#define HW_POWER_MINPWR_CLR	(0x00000028)
+#define HW_POWER_MINPWR_TOG	(0x0000002c)
+#define HW_POWER_MINPWR_ADDR	(REGS_POWER_BASE + 0x00000020)
+
+#define BP_POWER_MINPWR_RSRVD1	15
+#define BM_POWER_MINPWR_RSRVD1	0xFFFF8000
+#define BF_POWER_MINPWR_RSRVD1(v) \
+		(((v) << 15) & BM_POWER_MINPWR_RSRVD1)
+#define BM_POWER_MINPWR_LOWPWR_4P2	0x00004000
+#define BM_POWER_MINPWR_VDAC_DUMP_CTRL	0x00002000
+#define BM_POWER_MINPWR_PWD_BO	0x00001000
+#define BM_POWER_MINPWR_USE_VDDXTAL_VBG	0x00000800
+#define BM_POWER_MINPWR_PWD_ANA_CMPS	0x00000400
+#define BM_POWER_MINPWR_ENABLE_OSC	0x00000200
+#define BM_POWER_MINPWR_SELECT_OSC	0x00000100
+#define BM_POWER_MINPWR_VBG_OFF	0x00000080
+#define BM_POWER_MINPWR_DOUBLE_FETS	0x00000040
+#define BM_POWER_MINPWR_HALF_FETS	0x00000020
+#define BM_POWER_MINPWR_LESSANA_I	0x00000010
+#define BM_POWER_MINPWR_PWD_XTAL24	0x00000008
+#define BM_POWER_MINPWR_DC_STOPCLK	0x00000004
+#define BM_POWER_MINPWR_EN_DC_PFM	0x00000002
+#define BM_POWER_MINPWR_DC_HALFCLK	0x00000001
+
+#define HW_POWER_CHARGE	(0x00000030)
+#define HW_POWER_CHARGE_SET	(0x00000034)
+#define HW_POWER_CHARGE_CLR	(0x00000038)
+#define HW_POWER_CHARGE_TOG	(0x0000003c)
+#define HW_POWER_CHARGE_ADDR	(REGS_POWER_BASE + 0x00000030)
+
+#define BP_POWER_CHARGE_RSRVD4	27
+#define BM_POWER_CHARGE_RSRVD4	0xF8000000
+#define BF_POWER_CHARGE_RSRVD4(v) \
+		(((v) << 27) & BM_POWER_CHARGE_RSRVD4)
+#define BP_POWER_CHARGE_ADJ_VOLT	24
+#define BM_POWER_CHARGE_ADJ_VOLT	0x07000000
+#define BF_POWER_CHARGE_ADJ_VOLT(v)  \
+		(((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT)
+#define BM_POWER_CHARGE_RSRVD3	0x00800000
+#define BM_POWER_CHARGE_ENABLE_LOAD	0x00400000
+#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS	0x00200000
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT	0x00100000
+#define BM_POWER_CHARGE_CHRG_STS_OFF	0x00080000
+#define BM_POWER_CHARGE_LIION_4P1	0x00040000
+#define BM_POWER_CHARGE_USE_EXTERN_R	0x00020000
+#define BM_POWER_CHARGE_PWD_BATTCHRG	0x00010000
+#define BP_POWER_CHARGE_RSRVD2	12
+#define BM_POWER_CHARGE_RSRVD2	0x0000F000
+#define BF_POWER_CHARGE_RSRVD2(v)  \
+		(((v) << 12) & BM_POWER_CHARGE_RSRVD2)
+#define BP_POWER_CHARGE_STOP_ILIMIT	8
+#define BM_POWER_CHARGE_STOP_ILIMIT	0x00000F00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v)  \
+		(((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT)
+#define BP_POWER_CHARGE_RSRVD1	6
+#define BM_POWER_CHARGE_RSRVD1	0x000000C0
+#define BF_POWER_CHARGE_RSRVD1(v)  \
+		(((v) << 6) & BM_POWER_CHARGE_RSRVD1)
+#define BP_POWER_CHARGE_BATTCHRG_I	0
+#define BM_POWER_CHARGE_BATTCHRG_I	0x0000003F
+#define BF_POWER_CHARGE_BATTCHRG_I(v)  \
+		(((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I)
+
+#define HW_POWER_VDDDCTRL	(0x00000040)
+#define HW_POWER_VDDDCTRL_ADDR	(REGS_POWER_BASE + 0x00000040)
+
+#define BP_POWER_VDDDCTRL_ADJTN	28
+#define BM_POWER_VDDDCTRL_ADJTN	0xF0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v) \
+		(((v) << 28) & BM_POWER_VDDDCTRL_ADJTN)
+#define BP_POWER_VDDDCTRL_RSRVD4	24
+#define BM_POWER_VDDDCTRL_RSRVD4	0x0F000000
+#define BF_POWER_VDDDCTRL_RSRVD4(v)  \
+		(((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4)
+#define BM_POWER_VDDDCTRL_PWDN_BRNOUT	0x00800000
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING	0x00400000
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG	0x00200000
+#define BM_POWER_VDDDCTRL_DISABLE_FET	0x00100000
+#define BP_POWER_VDDDCTRL_RSRVD3	18
+#define BM_POWER_VDDDCTRL_RSRVD3	0x000C0000
+#define BF_POWER_VDDDCTRL_RSRVD3(v)  \
+		(((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3)
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET	16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET	0x00030000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)  \
+		(((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET)
+#define BP_POWER_VDDDCTRL_RSRVD2	11
+#define BM_POWER_VDDDCTRL_RSRVD2	0x0000F800
+#define BF_POWER_VDDDCTRL_RSRVD2(v)  \
+		(((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2)
+#define BP_POWER_VDDDCTRL_BO_OFFSET	8
+#define BM_POWER_VDDDCTRL_BO_OFFSET	0x00000700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v)  \
+		(((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET)
+#define BP_POWER_VDDDCTRL_RSRVD1	5
+#define BM_POWER_VDDDCTRL_RSRVD1	0x000000E0
+#define BF_POWER_VDDDCTRL_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1)
+#define BP_POWER_VDDDCTRL_TRG	0
+#define BM_POWER_VDDDCTRL_TRG	0x0000001F
+#define BF_POWER_VDDDCTRL_TRG(v)  \
+		(((v) << 0) & BM_POWER_VDDDCTRL_TRG)
+
+#define HW_POWER_VDDACTRL	(0x00000050)
+#define HW_POWER_VDDACTRL_ADDR	(REGS_POWER_BASE + 0x00000050)
+
+#define BP_POWER_VDDACTRL_RSRVD4	20
+#define BM_POWER_VDDACTRL_RSRVD4	0xFFF00000
+#define BF_POWER_VDDACTRL_RSRVD4(v) \
+		(((v) << 20) & BM_POWER_VDDACTRL_RSRVD4)
+#define BM_POWER_VDDACTRL_PWDN_BRNOUT	0x00080000
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING	0x00040000
+#define BM_POWER_VDDACTRL_ENABLE_LINREG	0x00020000
+#define BM_POWER_VDDACTRL_DISABLE_FET	0x00010000
+#define BP_POWER_VDDACTRL_RSRVD3	14
+#define BM_POWER_VDDACTRL_RSRVD3	0x0000C000
+#define BF_POWER_VDDACTRL_RSRVD3(v)  \
+		(((v) << 14) & BM_POWER_VDDACTRL_RSRVD3)
+#define BP_POWER_VDDACTRL_LINREG_OFFSET	12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET	0x00003000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)  \
+		(((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET)
+#define BM_POWER_VDDACTRL_RSRVD2	0x00000800
+#define BP_POWER_VDDACTRL_BO_OFFSET	8
+#define BM_POWER_VDDACTRL_BO_OFFSET	0x00000700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v)  \
+		(((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET)
+#define BP_POWER_VDDACTRL_RSRVD1	5
+#define BM_POWER_VDDACTRL_RSRVD1	0x000000E0
+#define BF_POWER_VDDACTRL_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_VDDACTRL_RSRVD1)
+#define BP_POWER_VDDACTRL_TRG	0
+#define BM_POWER_VDDACTRL_TRG	0x0000001F
+#define BF_POWER_VDDACTRL_TRG(v)  \
+		(((v) << 0) & BM_POWER_VDDACTRL_TRG)
+
+#define HW_POWER_VDDIOCTRL	(0x00000060)
+#define HW_POWER_VDDIOCTRL_ADDR	(REGS_POWER_BASE + 0x00000060)
+
+#define BP_POWER_VDDIOCTRL_RSRVD5	24
+#define BM_POWER_VDDIOCTRL_RSRVD5	0xFF000000
+#define BF_POWER_VDDIOCTRL_RSRVD5(v) \
+		(((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5)
+#define BP_POWER_VDDIOCTRL_ADJTN	20
+#define BM_POWER_VDDIOCTRL_ADJTN	0x00F00000
+#define BF_POWER_VDDIOCTRL_ADJTN(v)  \
+		(((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN)
+#define BM_POWER_VDDIOCTRL_RSRVD4	0x00080000
+#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT	0x00040000
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING	0x00020000
+#define BM_POWER_VDDIOCTRL_DISABLE_FET	0x00010000
+#define BP_POWER_VDDIOCTRL_RSRVD3	14
+#define BM_POWER_VDDIOCTRL_RSRVD3	0x0000C000
+#define BF_POWER_VDDIOCTRL_RSRVD3(v)  \
+		(((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3)
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET	12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET	0x00003000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)  \
+		(((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET)
+#define BM_POWER_VDDIOCTRL_RSRVD2	0x00000800
+#define BP_POWER_VDDIOCTRL_BO_OFFSET	8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET	0x00000700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)  \
+		(((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET)
+#define BP_POWER_VDDIOCTRL_RSRVD1	5
+#define BM_POWER_VDDIOCTRL_RSRVD1	0x000000E0
+#define BF_POWER_VDDIOCTRL_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1)
 #define BP_POWER_VDDIOCTRL_TRG	0
-
-#define HW_POWER_STS		0xC0
-#define BM_POWER_STS_VBUSVALID	0x00000002
-#define BM_POWER_STS_BVALID	0x00000004
-#define BM_POWER_STS_AVALID	0x00000008
+#define BM_POWER_VDDIOCTRL_TRG	0x0000001F
+#define BF_POWER_VDDIOCTRL_TRG(v)  \
+		(((v) << 0) & BM_POWER_VDDIOCTRL_TRG)
+
+#define HW_POWER_VDDMEMCTRL	(0x00000070)
+#define HW_POWER_VDDMEMCTRL_ADDR	(REGS_POWER_BASE + 0x00000070)
+
+#define BP_POWER_VDDMEMCTRL_RSRVD2	11
+#define BM_POWER_VDDMEMCTRL_RSRVD2	0xFFFFF800
+#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \
+		(((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2)
+#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE	0x00000400
+#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT	0x00000200
+#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG	0x00000100
+#define BP_POWER_VDDMEMCTRL_RSRVD1	5
+#define BM_POWER_VDDMEMCTRL_RSRVD1	0x000000E0
+#define BF_POWER_VDDMEMCTRL_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_VDDMEMCTRL_RSRVD1)
+#define BP_POWER_VDDMEMCTRL_TRG	0
+#define BM_POWER_VDDMEMCTRL_TRG	0x0000001F
+#define BF_POWER_VDDMEMCTRL_TRG(v)  \
+		(((v) << 0) & BM_POWER_VDDMEMCTRL_TRG)
+
+#define HW_POWER_DCDC4P2	(0x00000080)
+#define HW_POWER_DCDC4P2_ADDR	(REGS_POWER_BASE + 0x00000080)
+
+#define BP_POWER_DCDC4P2_DROPOUT_CTRL	28
+#define BM_POWER_DCDC4P2_DROPOUT_CTRL	0xF0000000
+#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \
+		(((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL)
+#define BP_POWER_DCDC4P2_RSRVD5	26
+#define BM_POWER_DCDC4P2_RSRVD5	0x0C000000
+#define BF_POWER_DCDC4P2_RSRVD5(v)  \
+		(((v) << 26) & BM_POWER_DCDC4P2_RSRVD5)
+#define BP_POWER_DCDC4P2_ISTEAL_THRESH	24
+#define BM_POWER_DCDC4P2_ISTEAL_THRESH	0x03000000
+#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v)  \
+		(((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH)
+#define BM_POWER_DCDC4P2_ENABLE_4P2	0x00800000
+#define BM_POWER_DCDC4P2_ENABLE_DCDC	0x00400000
+#define BM_POWER_DCDC4P2_HYST_DIR	0x00200000
+#define BM_POWER_DCDC4P2_HYST_THRESH	0x00100000
+#define BM_POWER_DCDC4P2_RSRVD3	0x00080000
+#define BP_POWER_DCDC4P2_TRG	16
+#define BM_POWER_DCDC4P2_TRG	0x00070000
+#define BF_POWER_DCDC4P2_TRG(v)  \
+		(((v) << 16) & BM_POWER_DCDC4P2_TRG)
+#define BP_POWER_DCDC4P2_RSRVD2	13
+#define BM_POWER_DCDC4P2_RSRVD2	0x0000E000
+#define BF_POWER_DCDC4P2_RSRVD2(v)  \
+		(((v) << 13) & BM_POWER_DCDC4P2_RSRVD2)
+#define BP_POWER_DCDC4P2_BO	8
+#define BM_POWER_DCDC4P2_BO	0x00001F00
+#define BF_POWER_DCDC4P2_BO(v)  \
+		(((v) << 8) & BM_POWER_DCDC4P2_BO)
+#define BP_POWER_DCDC4P2_RSRVD1	5
+#define BM_POWER_DCDC4P2_RSRVD1	0x000000E0
+#define BF_POWER_DCDC4P2_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_DCDC4P2_RSRVD1)
+#define BP_POWER_DCDC4P2_CMPTRIP	0
+#define BM_POWER_DCDC4P2_CMPTRIP	0x0000001F
+#define BF_POWER_DCDC4P2_CMPTRIP(v)  \
+		(((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP)
+
+#define HW_POWER_MISC	(0x00000090)
+#define HW_POWER_MISC_ADDR	(REGS_POWER_BASE + 0x00000090)
+
+#define BP_POWER_MISC_RSRVD2	7
+#define BM_POWER_MISC_RSRVD2	0xFFFFFF80
+#define BF_POWER_MISC_RSRVD2(v) \
+		(((v) << 7) & BM_POWER_MISC_RSRVD2)
+#define BP_POWER_MISC_FREQSEL	4
+#define BM_POWER_MISC_FREQSEL	0x00000070
+#define BF_POWER_MISC_FREQSEL(v)  \
+		(((v) << 4) & BM_POWER_MISC_FREQSEL)
+#define BM_POWER_MISC_RSRVD1	0x00000008
+#define BM_POWER_MISC_DELAY_TIMING	0x00000004
+#define BM_POWER_MISC_TEST	0x00000002
+#define BM_POWER_MISC_SEL_PLLCLK	0x00000001
+
+#define HW_POWER_DCLIMITS	(0x000000a0)
+#define HW_POWER_DCLIMITS_ADDR	(REGS_POWER_BASE + 0x000000a0)
+
+#define BP_POWER_DCLIMITS_RSRVD3	16
+#define BM_POWER_DCLIMITS_RSRVD3	0xFFFF0000
+#define BF_POWER_DCLIMITS_RSRVD3(v) \
+		(((v) << 16) & BM_POWER_DCLIMITS_RSRVD3)
+#define BM_POWER_DCLIMITS_RSRVD2	0x00008000
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK	8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK	0x00007F00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)  \
+		(((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK)
+#define BM_POWER_DCLIMITS_RSRVD1	0x00000080
+#define BP_POWER_DCLIMITS_NEGLIMIT	0
+#define BM_POWER_DCLIMITS_NEGLIMIT	0x0000007F
+#define BF_POWER_DCLIMITS_NEGLIMIT(v)  \
+		(((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT)
+
+#define HW_POWER_LOOPCTRL	(0x000000b0)
+#define HW_POWER_LOOPCTRL_SET	(0x000000b4)
+#define HW_POWER_LOOPCTRL_CLR	(0x000000b8)
+#define HW_POWER_LOOPCTRL_TOG	(0x000000bc)
+#define HW_POWER_LOOPCTRL_ADDR	(REGS_POWER_BASE + 0x000000b0)
+
+#define BP_POWER_LOOPCTRL_RSRVD3	21
+#define BM_POWER_LOOPCTRL_RSRVD3	0xFFE00000
+#define BF_POWER_LOOPCTRL_RSRVD3(v) \
+		(((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3)
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF	0x00100000
+#define BM_POWER_LOOPCTRL_HYST_SIGN	0x00080000
+#define BM_POWER_LOOPCTRL_EN_CM_HYST	0x00040000
+#define BM_POWER_LOOPCTRL_EN_DF_HYST	0x00020000
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH	0x00010000
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH	0x00008000
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH	0x00004000
+#define BP_POWER_LOOPCTRL_EN_RCSCALE	12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE	0x00003000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)  \
+		(((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE)
+#define BM_POWER_LOOPCTRL_RSRVD2	0x00000800
+#define BP_POWER_LOOPCTRL_DC_FF	8
+#define BM_POWER_LOOPCTRL_DC_FF	0x00000700
+#define BF_POWER_LOOPCTRL_DC_FF(v)  \
+		(((v) << 8) & BM_POWER_LOOPCTRL_DC_FF)
+#define BP_POWER_LOOPCTRL_DC_R	4
+#define BM_POWER_LOOPCTRL_DC_R	0x000000F0
+#define BF_POWER_LOOPCTRL_DC_R(v)  \
+		(((v) << 4) & BM_POWER_LOOPCTRL_DC_R)
+#define BP_POWER_LOOPCTRL_RSRVD1	2
+#define BM_POWER_LOOPCTRL_RSRVD1	0x0000000C
+#define BF_POWER_LOOPCTRL_RSRVD1(v)  \
+		(((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1)
+#define BP_POWER_LOOPCTRL_DC_C	0
+#define BM_POWER_LOOPCTRL_DC_C	0x00000003
+#define BF_POWER_LOOPCTRL_DC_C(v)  \
+		(((v) << 0) & BM_POWER_LOOPCTRL_DC_C)
+
+#define HW_POWER_STS	(0x000000c0)
+#define HW_POWER_STS_ADDR	(REGS_POWER_BASE + 0x000000c0)
+
+#define BP_POWER_STS_RSRVD3	30
+#define BM_POWER_STS_RSRVD3	0xC0000000
+#define BF_POWER_STS_RSRVD3(v) \
+		(((v) << 30) & BM_POWER_STS_RSRVD3)
+#define BP_POWER_STS_PWRUP_SOURCE	24
+#define BM_POWER_STS_PWRUP_SOURCE	0x3F000000
+#define BF_POWER_STS_PWRUP_SOURCE(v)  \
+		(((v) << 24) & BM_POWER_STS_PWRUP_SOURCE)
+#define BP_POWER_STS_RSRVD2	22
+#define BM_POWER_STS_RSRVD2	0x00C00000
+#define BF_POWER_STS_RSRVD2(v)  \
+		(((v) << 22) & BM_POWER_STS_RSRVD2)
+#define BP_POWER_STS_PSWITCH	20
+#define BM_POWER_STS_PSWITCH	0x00300000
+#define BF_POWER_STS_PSWITCH(v)  \
+		(((v) << 20) & BM_POWER_STS_PSWITCH)
+#define BP_POWER_STS_RSRVD1	18
+#define BM_POWER_STS_RSRVD1	0x000C0000
+#define BF_POWER_STS_RSRVD1(v)  \
+		(((v) << 18) & BM_POWER_STS_RSRVD1)
+#define BM_POWER_STS_AVALID_STATUS	0x00020000
+#define BM_POWER_STS_BVALID_STATUS	0x00010000
+#define BM_POWER_STS_VBUSVALID_STATUS	0x00008000
+#define BM_POWER_STS_SESSEND_STATUS	0x00004000
+#define BM_POWER_STS_BATT_BO	0x00002000
+#define BM_POWER_STS_VDD5V_FAULT	0x00001000
+#define BM_POWER_STS_CHRGSTS	0x00000800
+#define BM_POWER_STS_DCDC_4P2_BO	0x00000400
 #define BM_POWER_STS_DC_OK	0x00000200
-
-#define HW_POWER_RESET		0x100
-
-#define HW_POWER_DEBUG		0x110
-#define BM_POWER_DEBUG_BVALIDPIOLOCK	0x00000002
-#define BM_POWER_DEBUG_AVALIDPIOLOCK	0x00000004
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK	0x00000008
-
-#define BP_POWER_STS_PSWITCH      20
-#define BM_POWER_STS_PSWITCH 0x00300000
-#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000
-
-#define BM_POWER_CTRL_CLKGATE 0x40000000
-#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000
-#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000
-#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000
-#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000
-#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000
-#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
-#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000
-#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000
-#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
-#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000
-#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000
-#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000
-#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000
-#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000
-#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800
-#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400
-#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200
-#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100
-#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080
-#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040
-#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020
-#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010
-#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008
-#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004
-#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
-
-#define BP_POWER_5VCTRL_VBUSDROOP_TRSH      28
-#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000
-#define BP_POWER_5VCTRL_HEADROOM_ADJ      24
-#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000
-#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00100000
-#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT      12
-#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000
-#define BP_POWER_5VCTRL_VBUSVALID_TRSH      8
-#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700
-#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080
-#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
-#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020
-#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010
-#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008
-#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004
-#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002
-#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001
-
-#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000
-#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000
-#define BM_POWER_MINPWR_PWD_BO 0x00001000
-#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800
-#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400
-#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200
-#define BM_POWER_MINPWR_SELECT_OSC 0x00000100
-#define BM_POWER_MINPWR_VBG_OFF 0x00000080
-#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040
-#define BM_POWER_MINPWR_HALF_FETS 0x00000020
-#define BM_POWER_MINPWR_LESSANA_I 0x00000010
-#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008
-#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004
-#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002
-#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001
-
-#define BP_POWER_CHARGE_ADJ_VOLT      24
-#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000
-#define BM_POWER_CHARGE_RSRVD3 0x00800000
-#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000
-#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 0x00200000
-#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000
-#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000
-#define BM_POWER_CHARGE_USE_EXTERN_R 0x00020000
-#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000
-#define BP_POWER_CHARGE_STOP_ILIMIT      8
-#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00
-#define BP_POWER_CHARGE_BATTCHRG_I      0
-#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F
-
-#define BP_POWER_VDDDCTRL_ADJTN      28
-#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000
-#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000
-#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000
-#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000
-#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000
-#define BP_POWER_VDDDCTRL_LINREG_OFFSET      16
-#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000
-#define BP_POWER_VDDDCTRL_BO_OFFSET      8
-#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700
-#define BP_POWER_VDDDCTRL_TRG      0
-#define BM_POWER_VDDDCTRL_TRG 0x0000001F
-
-#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000
-#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000
-#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000
-#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000
-#define BP_POWER_VDDACTRL_LINREG_OFFSET      12
-#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000
-#define BP_POWER_VDDACTRL_BO_OFFSET      8
-#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700
-#define BP_POWER_VDDACTRL_TRG      0
-#define BM_POWER_VDDACTRL_TRG 0x0000001F
-
-#define BP_POWER_VDDIOCTRL_ADJTN      20
-#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000
-#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000
-#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000
-#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000
-#define BP_POWER_VDDIOCTRL_LINREG_OFFSET      12
-#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000
-#define BP_POWER_VDDIOCTRL_BO_OFFSET      8
-#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700
-#define BP_POWER_VDDIOCTRL_TRG      0
-#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
-
-#define HW_POWER_VDDMEMCTRL (REGS_POWER_BASE + 0x00000070)
-#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400
-#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200
-#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100
-#define BP_POWER_VDDMEMCTRL_TRG      0
-#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F
-
-#define HW_POWER_DCDC4P2 (REGS_POWER_BASE + 0x00000080)
-#define BP_POWER_DCDC4P2_DROPOUT_CTRL      28
-#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000
-
-#define BP_POWER_DCDC4P2_ISTEAL_THRESH      24
-#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000
-#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000
-#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000
-#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000
-#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000
-#define BP_POWER_DCDC4P2_TRG      16
-#define BM_POWER_DCDC4P2_TRG 0x00070000
-#define BP_POWER_DCDC4P2_BO      8
-#define BM_POWER_DCDC4P2_BO 0x00001F00
-#define BP_POWER_DCDC4P2_CMPTRIP      0
-#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F
-
-#define HW_POWER_MISC (REGS_POWER_BASE + 0x00000090)
-#define BP_POWER_MISC_FREQSEL      4
-#define BM_POWER_MISC_FREQSEL 0x00000070
-#define BM_POWER_MISC_RSRVD1 0x00000008
-#define BM_POWER_MISC_DELAY_TIMING 0x00000004
-#define BM_POWER_MISC_TEST 0x00000002
-#define BM_POWER_MISC_SEL_PLLCLK 0x00000001
-
-#define HW_POWER_DCLIMITS (REGS_POWER_BASE + 0x000000a0)
-#define BP_POWER_DCLIMITS_POSLIMIT_BUCK      8
-#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00
-#define BP_POWER_DCLIMITS_NEGLIMIT      0
-#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F
-
-#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000
-#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000
-#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000
-#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000
-#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000
-#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000
-#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000
-#define BP_POWER_LOOPCTRL_EN_RCSCALE      12
-#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000
-#define BP_POWER_LOOPCTRL_DC_FF      8
-#define BM_POWER_LOOPCTRL_DC_FF 0x00000700
-#define BP_POWER_LOOPCTRL_DC_R      4
-#define BM_POWER_LOOPCTRL_DC_R 0x000000F0
-#define BP_POWER_LOOPCTRL_DC_C      0
-#define BM_POWER_LOOPCTRL_DC_C 0x00000003
-
-#define BP_POWER_STS_PWRUP_SOURCE      24
-#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000
-#define BP_POWER_STS_PSWITCH      20
-#define BM_POWER_STS_PSWITCH 0x00300000
-#define BM_POWER_STS_AVALID_STATUS 0x00020000
-#define BM_POWER_STS_BVALID_STATUS 0x00010000
-#define BM_POWER_STS_VBUSVALID_STATUS 0x00008000
-#define BM_POWER_STS_SESSEND_STATUS 0x00004000
-#define BM_POWER_STS_BATT_BO 0x00002000
-#define BM_POWER_STS_VDD5V_FAULT 0x00001000
-#define BM_POWER_STS_CHRGSTS 0x00000800
-#define BM_POWER_STS_DCDC_4P2_BO 0x00000400
-#define BM_POWER_STS_DC_OK 0x00000200
-#define BM_POWER_STS_VDDIO_BO 0x00000100
-#define BM_POWER_STS_VDDA_BO 0x00000080
-#define BM_POWER_STS_VDDD_BO 0x00000040
-#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020
-#define BM_POWER_STS_VDD5V_DROOP 0x00000010
-#define BM_POWER_STS_AVALID 0x00000008
-#define BM_POWER_STS_BVALID 0x00000004
-#define BM_POWER_STS_VBUSVALID 0x00000002
-#define BM_POWER_STS_SESSEND 0x00000001
-
-#define HW_POWER_SPEED (REGS_POWER_BASE + 0x000000d0)
-#define BP_POWER_SPEED_STATUS      16
-#define BM_POWER_SPEED_STATUS 0x00FF0000
-#define BP_POWER_SPEED_CTRL      0
-#define BM_POWER_SPEED_CTRL 0x00000003
-
-#define HW_POWER_BATTMONITOR	0xe0
-#define BP_POWER_BATTMONITOR_BATT_VAL      16
-#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000
-#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400
-#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200
-#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100
-#define BP_POWER_BATTMONITOR_BRWNOUT_LVL      0
-#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F
-
-#define BP_POWER_RESET_UNLOCK      16
-#define BM_POWER_RESET_UNLOCK 0xFFFF0000
+#define BM_POWER_STS_VDDIO_BO	0x00000100
+#define BM_POWER_STS_VDDA_BO	0x00000080
+#define BM_POWER_STS_VDDD_BO	0x00000040
+#define BM_POWER_STS_VDD5V_GT_VDDIO	0x00000020
+#define BM_POWER_STS_VDD5V_DROOP	0x00000010
+#define BM_POWER_STS_AVALID	0x00000008
+#define BM_POWER_STS_BVALID	0x00000004
+#define BM_POWER_STS_VBUSVALID	0x00000002
+#define BM_POWER_STS_SESSEND	0x00000001
+
+#define HW_POWER_SPEED	(0x000000d0)
+#define HW_POWER_SPEED_SET	(0x000000d4)
+#define HW_POWER_SPEED_CLR	(0x000000d8)
+#define HW_POWER_SPEED_TOG	(0x000000dc)
+#define HW_POWER_SPEED_ADDR	(REGS_POWER_BASE + 0x000000d0)
+
+#define BP_POWER_SPEED_RSRVD1	24
+#define BM_POWER_SPEED_RSRVD1	0xFF000000
+#define BF_POWER_SPEED_RSRVD1(v) \
+		(((v) << 24) & BM_POWER_SPEED_RSRVD1)
+#define BP_POWER_SPEED_STATUS	16
+#define BM_POWER_SPEED_STATUS	0x00FF0000
+#define BF_POWER_SPEED_STATUS(v)  \
+		(((v) << 16) & BM_POWER_SPEED_STATUS)
+#define BP_POWER_SPEED_RSRVD0	2
+#define BM_POWER_SPEED_RSRVD0	0x0000FFFC
+#define BF_POWER_SPEED_RSRVD0(v)  \
+		(((v) << 2) & BM_POWER_SPEED_RSRVD0)
+#define BP_POWER_SPEED_CTRL	0
+#define BM_POWER_SPEED_CTRL	0x00000003
+#define BF_POWER_SPEED_CTRL(v)  \
+		(((v) << 0) & BM_POWER_SPEED_CTRL)
+
+#define HW_POWER_BATTMONITOR	(0x000000e0)
+#define HW_POWER_BATTMONITOR_ADDR	(REGS_POWER_BASE + 0x000000e0)
+
+#define BP_POWER_BATTMONITOR_RSRVD3	26
+#define BM_POWER_BATTMONITOR_RSRVD3	0xFC000000
+#define BF_POWER_BATTMONITOR_RSRVD3(v) \
+		(((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3)
+#define BP_POWER_BATTMONITOR_BATT_VAL	16
+#define BM_POWER_BATTMONITOR_BATT_VAL	0x03FF0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)  \
+		(((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL)
+#define BP_POWER_BATTMONITOR_RSRVD2	11
+#define BM_POWER_BATTMONITOR_RSRVD2	0x0000F800
+#define BF_POWER_BATTMONITOR_RSRVD2(v)  \
+		(((v) << 11) & BM_POWER_BATTMONITOR_RSRVD2)
+#define BM_POWER_BATTMONITOR_EN_BATADJ	0x00000400
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT	0x00000200
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD	0x00000100
+#define BP_POWER_BATTMONITOR_RSRVD1	5
+#define BM_POWER_BATTMONITOR_RSRVD1	0x000000E0
+#define BF_POWER_BATTMONITOR_RSRVD1(v)  \
+		(((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL	0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL	0x0000001F
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)  \
+		(((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL)
+
+#define HW_POWER_RESET	(0x00000100)
+#define HW_POWER_RESET_SET	(0x00000104)
+#define HW_POWER_RESET_CLR	(0x00000108)
+#define HW_POWER_RESET_TOG	(0x0000010c)
+#define HW_POWER_RESET_ADDR	(REGS_POWER_BASE + 0x00000100)
+
+#define BP_POWER_RESET_UNLOCK	16
+#define BM_POWER_RESET_UNLOCK	0xFFFF0000
+#define BF_POWER_RESET_UNLOCK(v) \
+		(((v) << 16) & BM_POWER_RESET_UNLOCK)
 #define BV_POWER_RESET_UNLOCK__KEY 0x3E77
-#define BM_POWER_RESET_PWD_OFF 0x00000002
-#define BM_POWER_RESET_PWD 0x00000001
-
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
-#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
-#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
-#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001
-
-#define HW_POWER_SPECIAL (REGS_POWER_BASE + 0x00000120)
-#define BP_POWER_SPECIAL_TEST      0
-#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF
-
-#define HW_POWER_VERSION (REGS_POWER_BASE + 0x00000130)
-#define BP_POWER_VERSION_MAJOR      24
-#define BM_POWER_VERSION_MAJOR 0xFF000000
-#define BP_POWER_VERSION_MINOR      16
-#define BM_POWER_VERSION_MINOR 0x00FF0000
-#define BP_POWER_VERSION_STEP      0
-#define BM_POWER_VERSION_STEP 0x0000FFFF
-
-#endif
+#define BP_POWER_RESET_RSRVD1	2
+#define BM_POWER_RESET_RSRVD1	0x0000FFFC
+#define BF_POWER_RESET_RSRVD1(v)  \
+		(((v) << 2) & BM_POWER_RESET_RSRVD1)
+#define BM_POWER_RESET_PWD_OFF	0x00000002
+#define BM_POWER_RESET_PWD	0x00000001
+
+#define HW_POWER_DEBUG	(0x00000110)
+#define HW_POWER_DEBUG_SET	(0x00000114)
+#define HW_POWER_DEBUG_CLR	(0x00000118)
+#define HW_POWER_DEBUG_TOG	(0x0000011c)
+#define HW_POWER_DEBUG_ADDR	(REGS_POWER_BASE + 0x00000110)
+
+#define BP_POWER_DEBUG_RSRVD0	4
+#define BM_POWER_DEBUG_RSRVD0	0xFFFFFFF0
+#define BF_POWER_DEBUG_RSRVD0(v) \
+		(((v) << 4) & BM_POWER_DEBUG_RSRVD0)
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK	0x00000008
+#define BM_POWER_DEBUG_AVALIDPIOLOCK	0x00000004
+#define BM_POWER_DEBUG_BVALIDPIOLOCK	0x00000002
+#define BM_POWER_DEBUG_SESSENDPIOLOCK	0x00000001
+
+#define HW_POWER_SPECIAL	(0x00000120)
+#define HW_POWER_SPECIAL_SET	(0x00000124)
+#define HW_POWER_SPECIAL_CLR	(0x00000128)
+#define HW_POWER_SPECIAL_TOG	(0x0000012c)
+#define HW_POWER_SPECIAL_ADDR	(REGS_POWER_BASE + 0x00000120)
+
+#define BP_POWER_SPECIAL_TEST	0
+#define BM_POWER_SPECIAL_TEST	0xFFFFFFFF
+#define BF_POWER_SPECIAL_TEST(v)	(v)
+
+#define HW_POWER_VERSION	(0x00000130)
+#define HW_POWER_VERSION_ADDR	(REGS_POWER_BASE + 0x00000130)
+
+#define BP_POWER_VERSION_MAJOR	24
+#define BM_POWER_VERSION_MAJOR	0xFF000000
+#define BF_POWER_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_POWER_VERSION_MAJOR)
+#define BP_POWER_VERSION_MINOR	16
+#define BM_POWER_VERSION_MINOR	0x00FF0000
+#define BF_POWER_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_POWER_VERSION_MINOR)
+#define BP_POWER_VERSION_STEP	0
+#define BM_POWER_VERSION_STEP	0x0000FFFF
+#define BF_POWER_VERSION_STEP(v)  \
+		(((v) << 0) & BM_POWER_VERSION_STEP)
+#endif /* __ARCH_ARM___POWER_H */