arm: tegra: soctherm: fix pskip bypass program

Fix PSKIP configuration in soctherm for T132 chipset.
Bypass ramp rate only in soctherm, but program the similar
registers in ccroc the same as before as in soctherm for
correct throttling behavior.

Also added a clear comment noting the restriction of mapping
throttling_depth string and actual throttle depth configuration
in T13x due to indirect vector-based throttle selection.

Change-Id: I86635101fc61229e54b22db67f134917e6a7e0aa
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/423359
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>

3 files changed, 32 insertions, 10 deletions

diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c
index c2d1ff69b9f5..accb119fab63 100644
--- a/arch/arm/mach-tegra/board-ardbeg-power.c
+++ b/arch/arm/mach-tegra/board-ardbeg-power.c
@@ -535,6 +535,19 @@ static struct soctherm_therm ardbeg_therm_pop[THERM_SIZE] = {
 	},
 };
 
+/*
+ * @PSKIP_CONFIG_NOTE: For T132, throttling config of PSKIP is no longer
+ * done in soctherm registers. These settings are now done via registers in
+ * denver:ccroc module which are at a different register offset. More
+ * importantly, there are _only_ three levels of throttling: 'low',
+ * 'medium' and 'heavy' and are selected via the 'throttling_depth' field
+ * in the throttle->devs[] section of the soctherm config. Since the depth
+ * specification is per device, it is necessary to manually make sure the
+ * depths specified alongwith a given level are the same across all devs,
+ * otherwise it will overwrite a previously set depth with a different
+ * depth. We will refer to this comment at each relevant location in the
+ * config sections below.
+ */
 static struct soctherm_platform_data ardbeg_soctherm_data = {
 	.oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
 	.num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
@@ -625,6 +638,7 @@ static struct soctherm_platform_data ardbeg_soctherm_data = {
 				[THROTTLE_DEV_CPU] = {
 					.enable = true,
 					.depth = 80,
+					/* see @PSKIP_CONFIG_NOTE */
 					.throttling_depth = "heavy_throttling",
 				},
 				[THROTTLE_DEV_GPU] = {
@@ -753,6 +767,7 @@ static struct soctherm_throttle battery_oc_throttle_t13x = {
 		[THROTTLE_DEV_CPU] = {
 			.enable = true,
 			.depth = 50,
+			/* see @PSKIP_CONFIG_NOTE */
 			.throttling_depth = "low_throttling",
 		},
 		[THROTTLE_DEV_GPU] = {
@@ -796,6 +811,7 @@ static struct soctherm_throttle voltmon_throttle_t13x = {
 			.divisor = 255,
 			.duration = 0,
 			.step = 0,
+			/* see @PSKIP_CONFIG_NOTE */
 			.throttling_depth = "medium_throttling",
 		},
 		[THROTTLE_DEV_GPU] = {
diff --git a/arch/arm/mach-tegra/board-norrin-power.c b/arch/arm/mach-tegra/board-norrin-power.c
index d3b25d96c59d..afcb16b5e830 100644
--- a/arch/arm/mach-tegra/board-norrin-power.c
+++ b/arch/arm/mach-tegra/board-norrin-power.c
@@ -272,6 +272,7 @@ static struct soctherm_platform_data norrin_soctherm_data = {
 				[THROTTLE_DEV_CPU] = {
 					.enable = true,
 					.depth = 80,
+			/* see @PSKIP_CONFIG_NOTE in board-ardbeg-power.c */
 					.throttling_depth = "heavy_throttling",
 				},
 				[THROTTLE_DEV_GPU] = {
diff --git a/arch/arm/mach-tegra/tegra11_soctherm.c b/arch/arm/mach-tegra/tegra11_soctherm.c
index 8661f5f1b1a8..bbe96a413788 100644
--- a/arch/arm/mach-tegra/tegra11_soctherm.c
+++ b/arch/arm/mach-tegra/tegra11_soctherm.c
@@ -2287,8 +2287,8 @@ static bool throttlectl_cpu_mn(enum soctherm_throttle_id throt)
  */
 static bool throttlectl_cpu_level(enum soctherm_throttle_id throt)
 {
-	u32 r, throt_vect = 0;
-	int throt_level = 0;
+	u32 r, throt_vect;
+	int throt_level;
 	struct soctherm_throttle *data = &plat_data.throttle[throt];
 	struct soctherm_throttle_dev *dev = &data->devs[THROTTLE_DEV_CPU];
 
@@ -2302,9 +2302,12 @@ static bool throttlectl_cpu_level(enum soctherm_throttle_id throt)
 	} else if (!strcmp(dev->throttling_depth, "medium_throttling")) {
 		throt_level = THROT_LEVEL_MED;
 		throt_vect = THROT_VECT_MED;
-	} else {
+	} else if (!strcmp(dev->throttling_depth, "low_throttling")) {
 		throt_level = THROT_LEVEL_LOW;
 		throt_vect = THROT_VECT_LOW;
+	} else {
+		throt_level = THROT_LEVEL_NONE;
+		throt_vect = THROT_VECT_NONE;
 	}
 
 	if (dev->depth)
@@ -2312,20 +2315,22 @@ static bool throttlectl_cpu_level(enum soctherm_throttle_id throt)
 
 	r = soctherm_readl(THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
 	r = REG_SET(r, THROT_PSKIP_CTRL_ENABLE, dev->enable);
-	/* for T132: setup throttle vector in soctherm register */
+	/* setup throttle vector in soctherm register */
 	r = REG_SET(r, THROT_PSKIP_CTRL_VECT_CPU, throt_vect);
 	r = REG_SET(r, THROT_PSKIP_CTRL_VECT2_CPU, throt_vect);
 	soctherm_writel(r, THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
 
-	/* No point programming the sequencer, since we're bypassing it */
-
-	/* for T132: setup actual depth in ccroc nv_therm register */
-	r = soctherm_readl(THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
-	r = REG_SET(r, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE, 1);
+	/* bypass sequencer in soc_therm as it is programmed in ccroc */
+	r = REG_SET(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE, 1);
 	soctherm_writel(r, THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
 
+	if (throt_level == THROT_LEVEL_NONE)
+		return true;
+
+	/* setup PSKIP in ccroc nv_therm registers */
 	r = clk_reset13_readl(THROT13_PSKIP_RAMP_CPU(throt_level));
-	r = REG_SET(r, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE, 1);
+	r = REG_SET(r, THROT_PSKIP_RAMP_DURATION, dev->duration);
+	r = REG_SET(r, THROT_PSKIP_RAMP_STEP, dev->step);
 	clk_reset13_writel(r, THROT13_PSKIP_RAMP_CPU(throt_level));
 
 	r = clk_reset13_readl(THROT13_PSKIP_CTRL_CPU(throt_level));