diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-06-26 15:14:30 -0700 |
|---|---|---|
| committer | Emad Mir <emir@nvidia.com> | 2014-07-08 18:59:00 -0700 |
| commit | f6340227e5abf042c8ff85119affc1ac1773eccb (patch) | |
| tree | a9f364ee2eb77d2438e2f17658b7794908ee742a /arch/arm | |
| parent | 11fc33400ff906c0a491065daeb7be973ab6e9a7 (diff) | |
ARM: tegra: dvfs: Update DFLL tune settings to P4v17
Added DFLL tune settings for new speedo ranges below 2180,
and 2180... 2336.
Bug 1442659
Change-Id: I8259d2e3de3ed5ca9b5a622700755711d82511f0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/429137
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/tegra13_dvfs.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/tegra13_dvfs.c b/arch/arm/mach-tegra/tegra13_dvfs.c index f41df2832b63..35c2d90ceba5 100644 --- a/arch/arm/mach-tegra/tegra13_dvfs.c +++ b/arch/arm/mach-tegra/tegra13_dvfs.c @@ -234,7 +234,6 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .dfll_tune_data = { .tune1 = 0x00000099, .droop_rate_min = 1000000, - .tune_high_min_millivolts = 900, .min_millivolts = 680, .tune_high_margin_mv = 30, }, @@ -736,13 +735,21 @@ static int round_voltage(int mv, struct rail_alignment *align, bool up) static void __init set_cpu_dfll_tuning_data(struct cpu_cvb_dvfs *d, int speedo) { if (d->speedo_id >= 1) { - if (speedo <= 2336) { - d->dfll_tune_data.tune0 = 0x8315FF; - d->dfll_tune_data.tune0_high_mv = 0x8340FF; - d->dfll_tune_data.tune0_simon_mask = 0x100000; + /* Initial (low SiMon grade) settings - same for all parts */ + d->dfll_tune_data.tune0 = 0x8315FF; + d->dfll_tune_data.tune0_high_mv = 0x8340FF; + + if (speedo <= 2180) { + /* Toggle SiMon mask - high grade settings 0x8A....*/ + d->dfll_tune_data.tune0_simon_mask = 0x090000; + d->dfll_tune_data.tune_high_min_millivolts = 950; + } else if (speedo < 2336) { + /* Toggle SiMon mask - high grade settings 0x87....*/ + d->dfll_tune_data.tune0_simon_mask = 0x040000; + d->dfll_tune_data.tune_high_min_millivolts = 900; } else { - d->dfll_tune_data.tune0 = 0x8315FF; - d->dfll_tune_data.tune0_high_mv = 0x8340FF; + /* High and low grade settings are the same */ + d->dfll_tune_data.tune_high_min_millivolts = 900; } } } |