diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2014-01-10 11:31:29 -0800 |
|---|---|---|
| committer | Krishna Reddy <vdumpa@nvidia.com> | 2014-03-10 16:19:49 -0700 |
| commit | 24b5e2d53a2895982ae8cb35398cf4c2610b58b4 (patch) | |
| tree | 8cbcfff5315e5ad37e2e2c69dfafa3d1566f542a /arch/arm | |
| parent | 918fa5def9fb9ec2ba608c95e06299debd2d9d89 (diff) | |
Revert "[ARM] mm: add memory type for inner-writeback"
This reverts commit b6e576d7370f64b78f828af495b1a21ffb56f887.
Change-Id: I872c3c06e7c8a5986ba5aed57fa9cd7ec7fa2f88
Reviewed-on: http://git-master/r/354411
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/pgtable-2level.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/pgtable.h | 3 | ||||
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7-2level.S | 4 | ||||
| -rw-r--r-- | arch/arm/mm/proc-xsc3.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/proc-xscale.S | 2 |
6 files changed, 5 insertions, 9 deletions
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 71eff3c67f49..f97ee02386ee 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -141,7 +141,6 @@ #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) -#define L_PTE_MT_INNER_WB (_AT(pteval_t, 0x05) << 2) /* 0101 (armv6, armv7) */ #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 41d3bd1089de..0957ac82e22e 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -133,9 +133,6 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN) #endif -#define pgprot_inner_writeback(prot) \ - __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB) - #endif /* __ASSEMBLY__ */ /* diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index fa829840ee16..e3c48a3fe063 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -127,7 +127,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB + .long 0x00 @ unused .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 3d1628452a38..cc454e6cd76e 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ -.equ PRRR, 0xff0a89a8 -.equ NMRR, 0xc0e044e0 +.equ PRRR, 0xff0a81a8 +.equ NMRR, 0xc0e040e0 /* * Macro for setting up the TTBRx and TTBCR registers. diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index d1c9c59c3231..e8efd83b6f25 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -381,7 +381,7 @@ cpu_xsc3_mt_table: .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB (not present?) + .long 0x00 @ unused .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) .long 0x00 @ unused diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 14b859554b3f..e766f889bfd6 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -491,7 +491,7 @@ cpu_xscale_mt_table: .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB + .long 0x00 @ unused .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused |