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authorJay Agarwal <jagarwal@nvidia.com>2012-03-09 17:51:02 +0530
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-03-22 03:53:15 -0700
commitf8de79d91f59794f07797672998897e6576b9161 (patch)
tree74be680ecad535357507f3bcd1365cc8d984fcf0 /arch/arm
parent9ebd05d7fc5212ffc162296ba1ec194001211538 (diff)
tegra:pcie: Correct pcie check link sequence
1. Removed mdelay in reset code since pci devices are not detected with this. 2. Moved the reset logic down in retry label. Bug 637871 Change-Id: Idd6344860e513407d5f8c8ba05e1beef0f39bf57 Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/89128 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/pcie.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 462142f88072..6a424365f42a 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -1040,13 +1040,6 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
int timeout;
do {
- /* Pulse the PEX reset */
- reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
- afi_writel(reg, reset_reg);
- mdelay(1);
- reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
- afi_writel(reg, reset_reg);
-
timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
while (timeout) {
reg = readl(pp->base + RP_VEND_XP);
@@ -1075,6 +1068,12 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
}
retry:
+ /* Pulse the PEX reset */
+ reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
+ afi_writel(reg, reset_reg);
+ reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
+ afi_writel(reg, reset_reg);
+
retries--;
} while (retries);