diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2013-12-21 11:11:37 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-09 21:33:30 +0800 |
| commit | dde5697332f35f994d209f286f6181dab15260a7 (patch) | |
| tree | ec09ce709af90adffab208e3911a499e140126be /arch/arm | |
| parent | a4f3ac4d2bde71da01d819c4d25b7f6b152a1324 (diff) | |
ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
This patch adds pin group for NAND Flash Controller.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index ab75b721bf39..73920a1e7634 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -223,10 +223,24 @@ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 >; }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; }; }; &nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; nand-bus-width = <8>; nand-ecc-mode = "hw"; nand-on-flash-bbt; |