ccwmx51: Fix compilation issues after applying Freescale patches

The mach-mx51 folder has been replaced by mach-mx5 to enable the addition
of more platforms.

Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>

27 files changed, 296 insertions, 6480 deletions

diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig
index 7ea1a91f4023..fdca0f6900ca 100644
--- a/arch/arm/mach-mx28/Kconfig
+++ b/arch/arm/mach-mx28/Kconfig
@@ -7,7 +7,6 @@ config MACH_MX28EVK
 	select USB_ARCH_HAS_EHCI
 
 config MXS_TIMER_WITH_MACH
-	bool
-	default y
+	bool "Timer with architecture."
 
 endchoice
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 5c07a3a5d2b6..cd6a985af260 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,10 +1,10 @@
 if ARCH_MX5
 
 config ARCH_MX51
-	bool
+	bool "MX51"
 
 config ARCH_MX53
-	bool
+	bool "MX53"
 
 config FORCE_MAX_ZONEORDER
     int "MAX_ORDER"
@@ -44,6 +44,25 @@ config MACH_MX53_EVK
 	  Include support for MX53 EVK platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MODULE_CCXMX51
+	bool
+
+config MACH_CCWMX51JS
+	bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board"
+	select MODULE_CCXMX51
+	help
+	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on the
+	  JumpStart Kit base board. This includes specific configurations for the
+	  peripherals on that base board.
+
+config MACH_CCWMX51
+	bool "Support for the ConnectCore Wi-i.MX51 module"
+	select MODULE_CCXMX51
+	help
+	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on a
+	  custom board. The machine file should be modified to include support for
+	  the interfaces available in that board.
+
 comment "MX5x Options:"
 
 config MXC_SDMA_API
@@ -76,3 +95,58 @@ config SDMA_IRAM
 	  Support Internal RAM as SDMA buffer or control structures
 
 endif
+
+menu "Serial Port Options"
+config UART1_ENABLED
+	bool "Enable UART1"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART1 interface
+
+config UART2_ENABLED
+	bool "Enable UART2"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART2 interface
+
+config UART3_ENABLED
+	bool "Enable UART3"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART3 interface
+endmenu
+
+menu "SPI Interface Options"
+config SPI_MXC_SELECT1
+	bool "Enable CSPI1"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default y
+	help
+	  Enable the CSPI1 interface
+
+config SPI_MXC_SELECT1_SS1
+	bool "Enable SS1 line for CSPI1"
+	depends on SPI_MXC_SELECT1 && MACH_CCWMX51JS
+	default y
+	help
+          Enable SS1 (slave select 1) line, used on ConnectCore Wi-i.MX51 base board SPI connector
+
+config SPI_MXC_SELECT2
+	bool "Enable CSPI2"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default n
+	help
+	  Enable the CSPI2 interface
+
+config SPI_MXC_SELECT3
+	bool "Enable CSPI3"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default n
+	help
+	  Enable the CSPI3 interface
+endmenu
+
+source "arch/arm/mach-mx5/displays/Kconfig"
\ No newline at end of file
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index cbf2137fd938..a04f5017b6d0 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -11,4 +11,5 @@ sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o susp
 obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o
-
+obj-$(CONFIG_MACH_CCWMX51JS) += mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o
+obj-$(CONFIG_MXC_PMIC_MC13892) +=  mx51_ccwmx51js_pmic_mc13892.o
diff --git a/arch/arm/mach-mx51/board-ccwmx51.h b/arch/arm/mach-mx5/board-ccwmx51.h
index 6696c27c5c36..6696c27c5c36 100644
--- a/arch/arm/mach-mx51/board-ccwmx51.h
+++ b/arch/arm/mach-mx5/board-ccwmx51.h
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index df433a8f5417..143ba48d2b2c 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -258,6 +258,13 @@ struct platform_device mxc_fb_devices[] = {
 	},
 };
 
+struct platform_device lcd_pdev = {
+        .name = "ccwmx51_display",
+        .dev = {
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
 static struct resource vpu_resources[] = {
 	{
 		.start = VPU_BASE_ADDR,
@@ -610,6 +617,70 @@ struct mxc_gpio_port mxc_gpio_ports[] = {
 	},
 };
 
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+static struct resource smsc911x_device_resources[] = {
+	{
+		.name	= "smsc911x-memory",
+		.start	= CS5_BASE_ADDR,
+		.end	= CS5_BASE_ADDR + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
+		.end	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smsc911x_device = {
+        .name             = "smsc911x",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(smsc911x_device_resources),
+        .resource         = smsc911x_device_resources,
+};
+
+/* WEIM registers */
+#define CSGCR1	0x00
+#define CSGCR2	0x04
+#define CSRCR1	0x08
+#define CSRCR2	0x0C
+#define CSWCR1	0x10
+
+static void ccwmx51_init_ext_eth_mac(void)
+{
+	__iomem u32 *weim_vbaddr;
+
+	weim_vbaddr = ioremap(WEIM_BASE_ADDR, SZ_4K);
+	if (weim_vbaddr == 0) {
+		printk(KERN_ERR "Unable to ioremap 0x%08x in %s\n", WEIM_BASE_ADDR, __func__);
+		return;
+	}
+
+	/** Configure the CS timming, bus width, etc.
+	 * 16 bit on DATA[31..16], not multiplexed, async
+	 * RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0, APR=0
+	 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0
+	 */
+	writel(0x00420081, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR1);
+	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR2);
+	writel(0x32260000, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR1);
+	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR2);
+	writel(0x72080f00, (unsigned int)(weim_vbaddr) + 0x78 + CSWCR1);
+
+	iounmap(weim_vbaddr);
+
+	/* Configure interrupt line as GPIO input, the iomux should be already setup */
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9), "LAN2-irq");
+	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9));
+}
+#endif
+
+#if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE)
+struct platform_device mxc_wm8753_device = {
+	.name = "ccwmx51js",
+};
+#endif
+
 int __init mxc_register_gpios(void)
 {
 	if (cpu_is_mx51())
@@ -1346,6 +1417,9 @@ int __init mxc_init_devices(void)
 
 	mxc_init_scc_iram();
 	mxc_init_gpu2d();
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+	ccwmx51_init_ext_eth_mac();
+#endif
 	return 0;
 }
 postcore_initcall(mxc_init_devices);
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index d3467faf90e1..e5effff9cedc 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -59,4 +59,5 @@ extern struct platform_device mxc_usbdr_otg_device;
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbh2_device;
-
+extern struct platform_device lcd_pdev;
+extern struct platform_device mxc_wm8753_device;
diff --git a/arch/arm/mach-mx51/displays/CUSTOM.h b/arch/arm/mach-mx5/displays/CUSTOM.h
index 19759533d84e..19759533d84e 100644
--- a/arch/arm/mach-mx51/displays/CUSTOM.h
+++ b/arch/arm/mach-mx5/displays/CUSTOM.h
diff --git a/arch/arm/mach-mx51/displays/Kconfig b/arch/arm/mach-mx5/displays/Kconfig
index 347f21cafd64..674a6651bcca 100644
--- a/arch/arm/mach-mx51/displays/Kconfig
+++ b/arch/arm/mach-mx5/displays/Kconfig
@@ -3,7 +3,7 @@
 # Copyright 2010 Digi International, Inc
 #
 
-if FB_MXC_SYNC_PANEL
+if FB_MXC_SYNC_PANEL && MACH_CCWMX51JS
 
 comment "Display selection"
 
diff --git a/arch/arm/mach-mx51/displays/LQ070Y3DG3B.h b/arch/arm/mach-mx5/displays/LQ070Y3DG3B.h
index 8cf33b65fd6b..8cf33b65fd6b 100644
--- a/arch/arm/mach-mx51/displays/LQ070Y3DG3B.h
+++ b/arch/arm/mach-mx5/displays/LQ070Y3DG3B.h
diff --git a/arch/arm/mach-mx51/displays/display-ccwmx51.h b/arch/arm/mach-mx5/displays/display-ccwmx51.h
index b1e875c9694f..b1e875c9694f 100644
--- a/arch/arm/mach-mx51/displays/display-ccwmx51.h
+++ b/arch/arm/mach-mx5/displays/display-ccwmx51.h
diff --git a/arch/arm/mach-mx51/displays/displays.h b/arch/arm/mach-mx5/displays/displays.h
index 1fa2c1d05b5d..1fa2c1d05b5d 100644
--- a/arch/arm/mach-mx51/displays/displays.h
+++ b/arch/arm/mach-mx5/displays/displays.h
diff --git a/arch/arm/mach-mx5/dummy_gpio.c b/arch/arm/mach-mx5/dummy_gpio.c
index 8d9537d31026..8eb771d29a06 100644
--- a/arch/arm/mach-mx5/dummy_gpio.c
+++ b/arch/arm/mach-mx5/dummy_gpio.c
@@ -14,12 +14,6 @@
 #include <linux/errno.h>
 #include <linux/module.h>
 
-void gpio_uart_active(int port, int no_irda) {}
-EXPORT_SYMBOL(gpio_uart_active);
-
-void gpio_uart_inactive(int port, int no_irda) {}
-EXPORT_SYMBOL(gpio_uart_inactive);
-
 void gpio_gps_active(void) {}
 EXPORT_SYMBOL(gpio_gps_active);
 
diff --git a/arch/arm/mach-mx51/mx51_ccwmx51js.c b/arch/arm/mach-mx5/mx51_ccwmx51js.c
index 453261160cd9..91ccc1dc81f5 100644
--- a/arch/arm/mach-mx51/mx51_ccwmx51js.c
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js.c
@@ -44,11 +44,12 @@
 #include <mach/gpio.h>
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
-#include "board.h"
+#include "board-ccwmx51.h"
 #include "iomux.h"
 #include "crm_regs.h"
 #include "devices.h"
-
+#include "mx51_pins.h"
+#include "displays/displays.h"
 #include <linux/smc911x.h>
 
 #if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
@@ -195,6 +196,14 @@ static struct mxc_mmc_platform_data mmc3_data = {
 };
 #endif
 
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static struct resource mxcfb_resources[] = {
+	[0] = {
+	       .flags = IORESOURCE_MEM,
+	       },
+};
+#endif
+
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
  * setup.c file very early on during kernel starts. It allows the user to
@@ -210,32 +219,73 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
 	char *str;
-	int size = SZ_512M - SZ_32M;
 	struct tag *t;
+	struct tag *mem_tag = 0;
+	int total_mem = SZ_512M;
+	int left_mem = 0;
+	int gpu_mem = SZ_64M;
+	int fb_mem = SZ_32M;
 
-	mxc_cpu_init();
+	mxc_set_cpu_type(MXC_CPU_MX51);
 
 	get_cpu_wp = mx51_get_cpu_wp;
 	set_num_cpu_wp = mx51_set_num_cpu_wp;
 
-	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_CMDLINE)
-			continue;
-		str = t->u.cmdline.cmdline;
-		str = strstr(str, "mem=");
-		if (str != NULL) {
-			str += 4;
-			size = memparse(str, &str);
-			if (size == 0 || size == SZ_512M)
-				return;
+	for_each_tag(mem_tag, tags) {
+		if (mem_tag->hdr.tag == ATAG_MEM) {
+			total_mem = mem_tag->u.mem.size;
+			left_mem = total_mem - gpu_mem - fb_mem;
+			break;
 		}
 	}
 
 	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_MEM)
-			continue;
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "mem=");
+			if (str != NULL) {
+				str += 4;
+				left_mem = memparse(str, &str);
+				if (left_mem == 0 || left_mem > total_mem)
+					left_mem = total_mem - gpu_mem - fb_mem;
+			}
+
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpu_memory=");
+			if (str != NULL) {
+				str += 11;
+				gpu_mem = memparse(str, &str);
+			}
+
+			break;
+		}
+	}
 
-		t->u.mem.size = size;
+	if (mem_tag) {
+		fb_mem = total_mem - left_mem - gpu_mem;
+		if (fb_mem < 0) {
+			gpu_mem = total_mem - left_mem;
+			fb_mem = 0;
+		}
+		mem_tag->u.mem.size = left_mem;
+
+		/*reserve memory for gpu*/
+		gpu_device.resource[5].start =
+				mem_tag->u.mem.start + left_mem;
+		gpu_device.resource[5].end =
+				gpu_device.resource[5].start + gpu_mem - 1;
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
+	defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+		if (fb_mem) {
+			mxcfb_resources[0].start =
+				gpu_device.resource[5].end + 1;
+			mxcfb_resources[0].end =
+				mxcfb_resources[0].start + fb_mem - 1;
+		} else {
+			mxcfb_resources[0].start = 0;
+			mxcfb_resources[0].end = 0;
+		}
+#endif
 	}
 }
 
@@ -424,8 +474,65 @@ static struct uio_info gpu2d_platform_data = {
 };
 #endif
 
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
 struct ccwmx51_lcd_pdata * plcd_platform_data;
 
+struct ccwmx51_lcd_pdata * ccwmx51_get_display(char *name)
+{
+#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) || defined(CONFIG_CCWMX51_CUSTOM)
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(lcd_display_list); i++)
+		if (!strncmp(lcd_display_list[i].fb_pdata.mode->name,
+			     name, strlen(lcd_display_list[i].fb_pdata.mode->name)))
+			return &lcd_display_list[i];
+#endif
+	return NULL;
+}
+
+static int __init ccwmx51_init_fb(void)
+{
+	char *options = NULL, *p;
+
+	if (fb_get_options("displayfb", &options))
+		pr_warning("no display information available in command line\n");
+
+	if (!options)
+		return -ENODEV;
+
+	if (!strncasecmp(options, "VGA", 3)) {
+		pr_info("VGA interface is primary\n");
+
+		/* Get the desired configuration provided by the bootloader */
+		if (options[3] != '@') {
+			pr_info("Video resolution for VGA interface not provided, using default\n");
+			/* TODO set default video here */
+		} else {
+			options = &options[4];
+			if (((p = strsep (&options, "@")) != NULL) && *p) {
+				if (!strcmp(p, "640x480x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "640x480M-16@60");
+				} else if (!strcmp(p, "800x600x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "800x600M-16@60");
+				} else if (!strcmp(p, "1024x768x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "1024x768M-16@60");
+				} else if (!strcmp(p, "1280x1024x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "1280x1024M-16@60");
+				} else
+					pr_warning("Unsuported video resolution: %s, using default\n", p);
+			}
+		}
+	} else {
+		if ((plcd_platform_data = ccwmx51_get_display(options)) != NULL) {
+			memcpy(&mx51_fb_data[0], &plcd_platform_data->fb_pdata, sizeof(struct mxc_fb_platform_data));
+			plcd_platform_data->vif = 0;	/* Select video interface 0 */
+		}
+	}
+	return 0;
+}
+device_initcall(ccwmx51_init_fb);
+#endif
+
 /*!
  * Board specific initialization.
  */
@@ -441,7 +548,6 @@ static void __init mxc_board_init(void)
 	mxc_cpu_common_init();
 	mxc_register_gpios();
 	ccwmx51_io_init();
-	early_console_setup(saved_command_line);
 
 	mxc_register_device(&mxc_wdt_device, NULL);
 	mxc_register_device(&mxcspi1_device, &mxcspi1_data);
@@ -504,6 +610,8 @@ static void __init mxc_board_init(void)
 	ccwmx51_init_i2c2();
 #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
 	mxc_register_device(&lcd_pdev, plcd_platform_data);
+	mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources);
+	mxc_fb_devices[0].resource = mxcfb_resources;
 	mxc_register_device(&mxc_fb_devices[0], &mx51_fb_data[0]);
 //	mxc_register_device(&mxc_fb_devices[1], &mx51_fb_data[1]);
 //	mxc_register_device(&mxc_fb_devices[2], NULL);
@@ -520,6 +628,8 @@ static void __init mxc_board_init(void)
 
 static void __init ccwmx51_timer_init(void)
 {
+	struct clk *uart_clk;
+
 	/* Change the CPU voltages for TO2*/
 	if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) {
 		cpu_wp_auto[0].cpu_voltage = 1175000;
@@ -528,6 +638,9 @@ static void __init ccwmx51_timer_init(void)
 	}
 
 	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+
+	uart_clk = clk_get(NULL, "uart_clk.1");
+	early_console_setup(UART2_BASE_ADDR, uart_clk);
 }
 
 static struct sys_timer mxc_timer = {
@@ -540,8 +653,8 @@ MACHINE_START(CCWMX51JS, "ConnectCore Wi-i.MX51 on a JSK board")
 	.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 	.boot_params = PHYS_OFFSET + 0x100,
 	.fixup = fixup_mxc_board,
-	.map_io = mx51_map_io,
-	.init_irq = mx51_init_irq,
+	.map_io = mx5_map_io,
+	.init_irq = mx5_init_irq,
 	.init_machine = mxc_board_init,
 	.timer = &mxc_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c
index 336eba686881..7922347f4f3e 100644
--- a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c
@@ -20,6 +20,7 @@
 #include <mach/gpio.h>
 
 #include "iomux.h"
+#include "mx51_pins.h"
 
 static void ccwmx51_mmc2_gpio_active(void);
 
@@ -380,7 +381,7 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_devices_pins[] = {
 #if defined(CONFIG_SND_SOC_WM8753) || defined(CONFIG_SND_SOC_WM8753_MODULE)
 static struct mxc_iomux_pin_cfg __initdata ccwmx51_audio_pins[] = {
 
-	/* TODO: the SSI interface should be selectable through configuration */  
+	/* TODO: the SSI interface should be selectable through configuration */
 	{	/* AUD3_BB_CK */
 		MX51_PIN_AUD3_BB_CK, IOMUX_CONFIG_ALT0 ,
 		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
@@ -543,11 +544,11 @@ void ccwmx51_gpio_spi_chipselect_inactive(int busnum, int ssb_pol,
 	case 1:
 		switch (chipselect) {
 		case 0x1:
-			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
 				       (ssb_pol & mask) ?  0 : 1);
 			break;
 		case 0x2:
-			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
 				       (ssb_pol & mask) ?  0 : 1);
 			break;
 		default:
diff --git a/arch/arm/mach-mx51/mx51_ccwmx51js_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_ccwmx51js_pmic_mc13892.c
index fd45b159bcfc..88864efe3b56 100644
--- a/arch/arm/mach-mx51/mx51_ccwmx51js_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js_pmic_mc13892.c
@@ -22,6 +22,7 @@
 #include <linux/mfd/mc13892/core.h>
 #include "iomux.h"
 #include <mach/irqs.h>
+#include "mx51_pins.h"
 
 /*
  * Convenience conversion.
diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
index e72ec58cbf3a..658583b65ab6 100644
--- a/arch/arm/mach-mx5/usb_dr.c
+++ b/arch/arm/mach-mx5/usb_dr.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include "usb.h"
 
+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC)
 static int usbotg_init_ext(struct platform_device *pdev);
 static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata);
 static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable);
@@ -137,6 +138,7 @@ static void usbotg_clock_gate(bool on)
 		clk_put(usb_clk);
 	}
 }
+#endif
 
 void __init mx5_usb_dr_init(void)
 {
diff --git a/arch/arm/mach-mx51/Kconfig b/arch/arm/mach-mx51/Kconfig
deleted file mode 100644
index 034e11d50c03..000000000000
--- a/arch/arm/mach-mx51/Kconfig
+++ /dev/null
@@ -1,148 +0,0 @@
-menu "MX51 Options"
-	depends on ARCH_MX51
-
-config FORCE_MAX_ZONEORDER
-    int "MAX_ORDER"
-    default "13"
-
-config MX51_OPTIONS
-	bool
-	default y
-	select CPU_V7
-	select USB_ARCH_HAS_EHCI
-	select MXC_TZIC
-
-config MACH_MX51_3DS
-	bool "Support MX51 3-Stack platforms"
-	default y
-	help
-	  Include support for MX51 3-Stack platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MACH_MX51_BABBAGE
-	bool "Support MX51 BABBAGE platforms"
-	help
-	  Include support for MX51 Babbage platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MODULE_CCXMX51
-	bool
-
-config MACH_CCWMX51JS
-	bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board"
-	select MODULE_CCXMX51
-	help
-	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on the
-	  JumpStart Kit base board. This includes specific configurations for the
-	  peripherals on that base board.
-
-config MACH_CCMX51JS
-	bool "Support for the ConnectCore i.MX51 module, on the JSK base board"
-	select MODULE_CCXMX51
-	help
-	  Include support for the Digi ConnectCore i.MX51 Embedded Module, on the
-	  JumpStart Kit base board. This includes specific configurations for the
-	  peripherals on that base board.
-
-config MACH_CCWMX51
-	bool "Support for the ConnectCore Wi-i.MX51 module"
-	select MODULE_CCXMX51
-	help
-	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on a
-	  custom board. The machine file should be modified to include support for
-	  the interfaces available in that board.
-
-config MACH_CCMX51
-	bool "Support for the ConnectCore i.MX51 module"
-	select MODULE_CCXMX51
-	help
-	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on a
-	  custom board. The machine file should be modified to include support for
-	  the interfaces available in that board.
-
-config MXC_SDMA_API
-        bool "Use SDMA API"
-        default y
-        help
-           This selects the Freescale MXC SDMA API.
-           If unsure, say N.
-
-config ARCH_MXC_HAS_NFC_V3
-        bool "MXC NFC Hardware Version 3"
-        depends on ARCH_MX51
-        default y
-        help
-           This selects the Freescale MXC Nand Flash Controller Hardware Version 3
-           If unsure, say N.
-
-config ARCH_MXC_HAS_NFC_V3_2
-        bool "MXC NFC Hardware Version 3.2"
-        depends on ARCH_MXC_HAS_NFC_V3
-        default y
-        help
-           This selects the Freescale MXC Nand Flash Controller Hardware Version 3.2
-           If unsure, say N.
-
-config SDMA_IRAM
-        bool "Use Internal RAM for SDMA transfer"
-        depends on MXC_SDMA_API
-	help
-           Support Internal RAM as SDMA buffer or control structures
-endmenu
-
-
-menu "Serial Port Options"
-config UART1_ENABLED
-	bool "Enable UART1"
-	default y
-	depends on SERIAL_MXC
-	help
-	  Enable the MX51 UART1 interface
-
-config UART2_ENABLED
-	bool "Enable UART2"
-	default y
-	depends on SERIAL_MXC
-	help
-	  Enable the MX51 UART2 interface
-
-config UART3_ENABLED
-	bool "Enable UART3"
-	default y
-	depends on SERIAL_MXC
-	help
-	  Enable the MX51 UART3 interface
-endmenu
-
-menu "SPI Interface Options"
-config SPI_MXC_SELECT1
-	bool "Enable CSPI1"
-	depends on SPI_MXC
-	default y
-	help
-	  Enable the CSPI1 interface
-
-config SPI_MXC_SELECT1_SS1
-	bool "Enable SS1 line for CSPI1"
-	depends on SPI_MXC_SELECT1
-	default y
-	help
-          Enable SS1 (slave select 1) line, used on ConnectCore Wi-i.MX51 base board SPI connector
-
-config SPI_MXC_SELECT2
-	bool "Enable CSPI2"
-	depends on SPI_MXC
-	default n
-	help
-	  Enable the CSPI2 interface
-
-config SPI_MXC_SELECT3
-	bool "Enable CSPI3"
-	depends on SPI_MXC
-	default n
-	help
-	  Enable the CSPI3 interface
-endmenu
-
-source "arch/arm/mach-mx51/displays/Kconfig"
-
diff --git a/arch/arm/mach-mx51/Makefile b/arch/arm/mach-mx51/Makefile
deleted file mode 100644
index 1ec448c03eef..000000000000
--- a/arch/arm/mach-mx51/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-
-obj-y   := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o pm.o sdram_autogating.o bus_freq.o
-
-obj-y   := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o pm.o sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o suspend.o
-
-obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o
-obj-$(CONFIG_MACH_CCWMX51JS) += mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o
-obj-$(CONFIG_MXC_PMIC_MC13892) +=  mx51_ccwmx51js_pmic_mc13892.o
-
diff --git a/arch/arm/mach-mx51/board.h b/arch/arm/mach-mx51/board.h
deleted file mode 100644
index e269ab46fb5a..000000000000
--- a/arch/arm/mach-mx51/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Digi International, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_H__
-#define __ASM_ARCH_MXC_BOARD_H__
-
-#if defined(CONFIG_MACH_CCWMX51JS) || defined(CONFIG_MACH_CCMX51JS) || \
-    defined(CONFIG_MACH_CCWMX51) || defined(CONFIG_MACH_CCMX51)
-#include "board-ccwmx51.h"
-#elif defined(MACH_MX51_3DS)
-#include "board-3stack.h"
-#elif defined(MACH_MX51_BABBAGE)
-#include "board-mx51_babbage.h"
-#endif
-
-#endif	/* __ASM_ARCH_MXC_BOARD_H__ */
diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c
deleted file mode 100644
index f88387af7048..000000000000
--- a/arch/arm/mach-mx51/clock.c
+++ /dev/null
@@ -1,3990 +0,0 @@
-/*
- * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/hrtimer.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <asm/io.h>
-#include <asm/div64.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-#include <mach/mxc_dvfs.h>
-#include <mach/sdram_autogating.h>
-
-#include "crm_regs.h"
-
-static struct clk pll1_main_clk;
-static struct clk pll1_sw_clk;
-static struct clk pll2_sw_clk;
-static struct clk pll3_sw_clk;
-static struct clk lp_apm_clk;
-static struct clk tve_clk;
-static struct clk emi_fast_clk;
-static struct clk emi_slow_clk;
-static struct clk emi_intr_clk;
-static struct clk ddr_clk;
-static struct clk ipu_clk[];
-static struct clk axi_a_clk;
-static struct clk axi_b_clk;
-static struct clk ddr_hf_clk;
-static struct clk mipi_hsp_clk;
-static struct clk gpu3d_clk;
-static struct clk gpu2d_clk;
-static struct clk vpu_clk[];
-static int cpu_curr_wp;
-static struct cpu_wp *cpu_wp_tbl;
-
-void __iomem *pll1_base;
-void __iomem *pll2_base;
-void __iomem *pll3_base;
-
-int cpu_wp_nr;
-int lp_high_freq;
-int lp_med_freq;
-
-#define SPIN_DELAY	1000000 /* in nanoseconds */
-
-extern int mxc_jtag_enabled;
-extern int uart_at_24;
-extern int cpufreq_trig_needed;
-extern int low_bus_freq_mode;
-
-static int cpu_clk_set_wp(int wp);
-extern void propagate_rate(struct clk *tclk);
-struct cpu_wp *(*get_cpu_wp)(int *wp);
-void (*set_num_cpu_wp)(int num);
-
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
-{
-	u32 min_pre, temp_pre, old_err, err;
-
-	if (div >= 512) {
-		*pre = 8;
-		*post = 64;
-	} else if (div >= 8) {
-		min_pre = (div - 1) / 64 + 1;
-		old_err = 8;
-		for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
-			err = div % temp_pre;
-			if (err == 0) {
-				*pre = temp_pre;
-				break;
-			}
-			err = temp_pre - err;
-			if (err < old_err) {
-				old_err = err;
-				*pre = temp_pre;
-			}
-		}
-		*post = (div + *pre - 1) / *pre;
-	} else if (div < 8) {
-		*pre = div;
-		*post = 1;
-	}
-}
-
-static int _clk_enable(struct clk *clk)
-{
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
-
-	if (clk->flags & AHB_HIGH_SET_POINT)
-		lp_high_freq++;
-	else if (clk->flags & AHB_MED_SET_POINT)
-		lp_med_freq++;
-
-
-	return 0;
-}
-
-static int _clk_enable_inrun(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
-	reg |= 1 << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
-	return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
-	__raw_writel(reg, clk->enable_reg);
-
-	if (clk->flags & AHB_HIGH_SET_POINT)
-		lp_high_freq--;
-	else if (clk->flags & AHB_MED_SET_POINT)
-		lp_med_freq--;
-}
-
-static void _clk_disable_inwait(struct clk *clk)
-{
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
-	reg |= 1 << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
-}
-
-/*
- * For the 4-to-1 muxed input clock
- */
-static inline u32 _get_mux(struct clk *parent, struct clk *m0,
-			   struct clk *m1, struct clk *m2, struct clk *m3)
-{
-	if (parent == m0)
-		return 0;
-	else if (parent == m1)
-		return 1;
-	else if (parent == m2)
-		return 2;
-	else if (parent == m3)
-		return 3;
-	else
-		BUG();
-
-	return 0;
-}
-
-/*
- * For the ddr muxed input clock
- */
-static inline u32 _get_mux_ddr(struct clk *parent, struct clk *m0,
-			   struct clk *m1, struct clk *m2, struct clk *m3, struct clk *m4)
-{
-	if (parent == m0)
-		return 0;
-	else if (parent == m1)
-		return 1;
-	else if (parent == m2)
-		return 2;
-	else if (parent == m3)
-		return 3;
-	else if (parent == m4)
-		return 4;
-	else
-		BUG();
-
-	return 0;
-}
-
-static inline void __iomem *_get_pll_base(struct clk *pll)
-{
-	if (pll == &pll1_main_clk)
-		return pll1_base;
-	else if (pll == &pll2_sw_clk)
-		return pll2_base;
-	else if (pll == &pll3_sw_clk)
-		return pll3_base;
-	else
-		BUG();
-
-	return NULL;
-}
-
-static struct clk ckih_clk = {
-	.name = "ckih",
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk ckih2_clk = {
-	.name = "ckih2",
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk osc_clk = {
-	.name = "osc",
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk ckil_clk = {
-	.name = "ckil",
-	.flags = RATE_PROPAGATES,
-};
-
-static void _fpm_recalc(struct clk *clk)
-{
-	clk->rate = ckil_clk.rate * 512;
-	if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0)
-		clk->rate *= 2;
-
-}
-
-static int _fpm_enable(struct clk *clk)
-{
-	u32 reg = __raw_readl(MXC_CCM_CCR);
-	reg |= MXC_CCM_CCR_FPM_EN;
-	__raw_writel(reg, MXC_CCM_CCR);
-	return 0;
-}
-
-static void _fpm_disable(struct clk *clk)
-{
-	u32 reg = __raw_readl(MXC_CCM_CCR);
-	reg &= ~MXC_CCM_CCR_FPM_EN;
-	__raw_writel(reg, MXC_CCM_CCR);
-}
-
-static struct clk fpm_clk = {
-	.name = "fpm_clk",
-	.parent = &ckil_clk,
-	.recalc = _fpm_recalc,
-	.enable = _fpm_enable,
-	.disable = _fpm_disable,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _fpm_div2_recalc(struct clk *clk)
-{
-	clk->rate = clk->parent->rate / 2;
-}
-
-static struct clk fpm_div2_clk = {
-	.name = "fpm_div2_clk",
-	.parent = &fpm_clk,
-	.recalc = _fpm_div2_recalc,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_pll_recalc(struct clk *clk)
-{
-	long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
-	unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
-	void __iomem *pllbase;
-	s64 temp;
-
-	pllbase = _get_pll_base(clk);
-
-	dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-	pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-	dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
-	if (pll_hfsm == 0) {
-		dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-	} else {
-		dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
-		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
-		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
-	}
-	pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-	mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
-	mfi = (mfi <= 5) ? 5 : mfi;
-	mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-	mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
-	/* Sign extend to 32-bits */
-	if (mfn >= 0x04000000) {
-		mfn |= 0xFC000000;
-		mfn_abs = -mfn;
-	}
-
-	ref_clk = 2 * clk->parent->rate;
-	if (dbl != 0)
-		ref_clk *= 2;
-
-	ref_clk /= (pdf + 1);
-	temp = (u64) ref_clk * mfn_abs;
-	do_div(temp, mfd + 1);
-	if (mfn < 0)
-		temp = -temp;
-	temp = (ref_clk * mfi) + temp;
-
-	clk->rate = temp;
-}
-
-static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, reg1;
-	void __iomem *pllbase;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	long mfi, pdf, mfn, mfd = 999999;
-	s64 temp64;
-	unsigned long quad_parent_rate;
-	unsigned long pll_hfsm, dp_ctl;
-
-	pllbase = _get_pll_base(clk);
-
-	quad_parent_rate = 4*clk->parent->rate;
-	pdf = mfi = -1;
-	while (++pdf < 16 && mfi < 5)
-		mfi = rate * (pdf+1) / quad_parent_rate;
-	if (mfi > 15)
-		return -1;
-	pdf--;
-
-	temp64 = rate*(pdf+1) - quad_parent_rate*mfi;
-	do_div(temp64, quad_parent_rate/1000000);
-	mfn = (long)temp64;
-
-	dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-	/* use dpdck0_2 */
-	__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
-	pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-	if (pll_hfsm == 0) {
-		reg = mfi<<4 | pdf;
-		__raw_writel(reg, pllbase + MXC_PLL_DP_OP);
-		__raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
-		__raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
-	} else {
-		reg = mfi<<4 | pdf;
-		__raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
-		__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
-		__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
-	}
-	/* If auto restart is disabled, restart the PLL and
-	  * wait for it to lock.
-	  */
-	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-	if (reg & MXC_PLL_DP_CTL_UPEN) {
-		reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG);
-		if (!(reg & MXC_PLL_DP_CONFIG_AREN)) {
-			reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-			reg1 |= MXC_PLL_DP_CTL_RST;
-			__raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
-		}
-		/* Wait for lock */
-		getnstimeofday(&nstimeofday);
-		while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
-					& MXC_PLL_DP_CTL_LRF)) {
-			getnstimeofday(&curtime);
-			if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-				panic("pll_set_rate: pll relock failed\n");
-		}
-	}
-	clk->rate = rate;
-	return 0;
-}
-
-static int _clk_pll_enable(struct clk *clk)
-{
-	u32 reg;
-	void __iomem *pllbase;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	pllbase = _get_pll_base(clk);
-	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
-	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
-	/* Wait for lock */
-	getnstimeofday(&nstimeofday);
-	while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("pll relock failed\n");
-	}
-	return 0;
-}
-
-static void _clk_pll_disable(struct clk *clk)
-{
-	u32 reg;
-	void __iomem *pllbase;
-
-	pllbase = _get_pll_base(clk);
-	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
-	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-static struct clk pll1_main_clk = {
-	.name = "pll1_main_clk",
-	.parent = &osc_clk,
-	.recalc = _clk_pll_recalc,
-	.enable = _clk_pll_enable,
-	.disable = _clk_pll_disable,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CCSR);
-
-	if (parent == &pll1_main_clk) {
-		reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-		__raw_writel(reg, MXC_CCM_CCSR);
-		/* Set the step_clk parent to be lp_apm, to save power. */
-		mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk,
-			       &pll3_sw_clk);
-		reg = __raw_readl(MXC_CCM_CCSR);
-		reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
-		    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-	} else {
-		if (parent == &lp_apm_clk) {
-			reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-			reg = __raw_readl(MXC_CCM_CCSR);
-			mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
-				       &pll3_sw_clk);
-			reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
-			    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-		} else {
-			mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
-				       &pll3_sw_clk);
-			reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
-			    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-			__raw_writel(reg, MXC_CCM_CCSR);
-			reg = __raw_readl(MXC_CCM_CCSR);
-			reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-
-		}
-	}
-	__raw_writel(reg, MXC_CCM_CCSR);
-
-	return 0;
-}
-
-static void _clk_pll1_sw_recalc(struct clk *clk)
-{
-	u32 reg, div;
-	div = 1;
-	reg = __raw_readl(MXC_CCM_CCSR);
-
-	if (clk->parent == &pll2_sw_clk) {
-		div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
-		       MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
-	} else if (clk->parent == &pll3_sw_clk) {
-		div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
-		       MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
-	}
-	clk->rate = clk->parent->rate / div;
-}
-
-/* pll1 switch clock */
-static struct clk pll1_sw_clk = {
-	.name = "pll1_sw_clk",
-	.parent = &pll1_main_clk,
-	.set_parent = _clk_pll1_sw_set_parent,
-	.recalc = _clk_pll1_sw_recalc,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CCSR);
-
-	if (parent == &pll2_sw_clk) {
-		reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-	} else {
-		reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL);
-		reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-	}
-	__raw_writel(reg, MXC_CCM_CCSR);
-	return 0;
-}
-
-/* same as pll2_main_clk. These two clocks should always be the same */
-static struct clk pll2_sw_clk = {
-	.name = "pll2",
-	.parent = &osc_clk,
-	.recalc = _clk_pll_recalc,
-	.enable = _clk_pll_enable,
-	.disable = _clk_pll_disable,
-	.set_rate = _clk_pll_set_rate,
-	.set_parent = _clk_pll2_sw_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-/* same as pll3_main_clk. These two clocks should always be the same */
-static struct clk pll3_sw_clk = {
-	.name = "pll3",
-	.parent = &osc_clk,
-	.set_rate = _clk_pll_set_rate,
-	.recalc = _clk_pll_recalc,
-	.enable = _clk_pll_enable,
-	.disable = _clk_pll_disable,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	if (parent == &osc_clk)
-		reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
-	else if (parent == &fpm_clk)
-		reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL;
-	else
-		return -EINVAL;
-
-	__raw_writel(reg, MXC_CCM_CCSR);
-
-	return 0;
-}
-
-static struct clk lp_apm_clk = {
-	.name = "lp_apm",
-	.parent = &osc_clk,
-	.set_parent = _clk_lp_apm_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_arm_recalc(struct clk *clk)
-{
-	u32 cacrr, div;
-
-	cacrr = __raw_readl(MXC_CCM_CACRR);
-	div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 i;
-	for (i = 0; i < cpu_wp_nr; i++) {
-		if (rate == cpu_wp_tbl[i].cpu_rate)
-			break;
-	}
-	if (i >= cpu_wp_nr)
-		return -EINVAL;
-	cpu_clk_set_wp(i);
-
-	return 0;
-}
-
-static unsigned long _clk_cpu_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 i;
-	u32 wp;
-
-	for (i = 0; i < cpu_wp_nr; i++) {
-		if (rate == cpu_wp_tbl[i].cpu_rate)
-			break;
-	}
-
-	if (i > cpu_wp_nr)
-		wp = 0;
-
-	return cpu_wp_tbl[wp].cpu_rate;
-}
-
-
-static struct clk cpu_clk = {
-	.name = "cpu_clk",
-	.parent = &pll1_sw_clk,
-	.recalc = _clk_arm_recalc,
-	.set_rate = _clk_cpu_set_rate,
-	.round_rate = _clk_cpu_round_rate,
-};
-
-static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
-
-	reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) &
-			MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("pll _clk_periph_apm_set_parent failed\n");
-	}
-	return 0;
-}
-
-static struct clk periph_apm_clk = {
-	.name = "periph_apm_clk",
-	.parent = &pll1_sw_clk,
-	.set_parent = _clk_periph_apm_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-/* TODO: Need to sync with GPC to determine if DVFS is in place so that
- * the DVFS_PODF divider can be applied in CDCR register.
- */
-static void _clk_main_bus_recalc(struct clk *clk)
-{
-	u32 div = 0;
-
-	if (dvfs_per_divider_active() || low_bus_freq_mode)
-		div  = (__raw_readl(MXC_CCM_CDCR) & 0x3);
-	clk->rate = clk->parent->rate / (div + 1);
-}
-
-static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	if (parent == &pll2_sw_clk) {
-		reg = __raw_readl(MXC_CCM_CBCDR) &
-		    ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-	} else if (parent == &periph_apm_clk) {
-		reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-	} else {
-		return -EINVAL;
-	}
-	__raw_writel(reg, MXC_CCM_CBCDR);
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static struct clk main_bus_clk = {
-	.name = "main_bus_clk",
-	.parent = &pll2_sw_clk,
-	.set_parent = _clk_main_bus_set_parent,
-	.recalc = _clk_main_bus_recalc,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_axi_a_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >>
-	       MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("pll _clk_axi_a_set_rate failed\n");
-	}
-	clk->rate = rate;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static unsigned long _clk_axi_a_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-
-static struct clk axi_a_clk = {
-	.name = "axi_a_clk",
-	.parent = &main_bus_clk,
-	.recalc = _clk_axi_a_recalc,
-	.set_rate = _clk_axi_a_set_rate,
-	.round_rate = _clk_axi_a_round_rate,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_ddr_hf_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
-	       MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static unsigned long _clk_ddr_hf_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_DDR_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_DDR_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_DDR_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("clk_ddr_hf_set_rate failed\n");
-	}
-	clk->rate = rate;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static struct clk ddr_hf_clk = {
-	.name = "ddr_hf_clk",
-	.parent = &pll1_sw_clk,
-	.recalc = _clk_ddr_hf_recalc,
-	.round_rate = _clk_ddr_hf_round_rate,
-	.set_rate = _clk_ddr_hf_set_rate,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_axi_b_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >>
-	       MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-
-	emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("_clk_axi_b_set_rate failed\n");
-	}
-
-	clk->rate = rate;
-	emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static unsigned long _clk_axi_b_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-
-static struct clk axi_b_clk = {
-	.name = "axi_b_clk",
-	.parent = &main_bus_clk,
-	.recalc = _clk_axi_b_recalc,
-	.set_rate = _clk_axi_b_set_rate,
-	.round_rate = _clk_axi_b_round_rate,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_ahb_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-	       MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-
-static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("_clk_ahb_set_rate failed\n");
-	}
-	clk->rate = rate;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static unsigned long _clk_ahb_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-
-static struct clk ahb_clk = {
-	.name = "ahb_clk",
-	.parent = &main_bus_clk,
-	.recalc = _clk_ahb_recalc,
-	.set_rate = _clk_ahb_set_rate,
-	.round_rate = _clk_ahb_round_rate,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_max_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-
-	/* Handshake with MAX when LPM is entered. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	return 0;
-}
-
-
-static void _clk_max_disable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_disable_inwait(clk);
-
-	/* No Handshake with MAX when LPM is entered as its disabled. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-
-static struct clk ahb_max_clk = {
-	.name = "max_clk",
-	.parent = &ahb_clk,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG14_OFFSET,
-	.enable = _clk_max_enable,
-	.disable = _clk_max_disable,
-};
-
-static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	if (parent == &ahb_clk) {
-		reg |= MXC_CCM_CBCDR_EMI_CLK_SEL;
-	} else if (parent == &main_bus_clk) {
-		reg &= ~MXC_CCM_CBCDR_EMI_CLK_SEL;
-	} else {
-		BUG();
-	}
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static void _clk_emi_slow_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
-	       MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
-			panic("_clk_emi_slow_set_rate failed\n");
-	}
-	clk->rate = rate;
-
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	return 0;
-}
-
-static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
-					      unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-
-static struct clk emi_slow_clk = {
-	.name = "emi_slow_clk",
-	.parent = &main_bus_clk,
-	.set_parent = _clk_emi_slow_set_parent,
-	.recalc = _clk_emi_slow_recalc,
-	.set_rate = _clk_emi_slow_set_rate,
-	.round_rate = _clk_emi_slow_round_rate,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG8_OFFSET,
-	.disable = _clk_disable_inwait,
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk ahbmux1_clk = {
-	.name = "ahbmux1_clk",
-	.id = 0,
-	.parent = &ahb_clk,
-	.secondary = &ahb_max_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG8_OFFSET,
-	.disable = _clk_disable_inwait,
-};
-
-static struct clk ahbmux2_clk = {
-	.name = "ahbmux2_clk",
-	.id = 0,
-	.parent = &ahb_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG9_OFFSET,
-	.disable = _clk_disable_inwait,
-};
-
-
-static struct clk emi_fast_clk = {
-	.name = "emi_fast_clk",
-	.parent = &ddr_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG7_OFFSET,
-	.disable = _clk_disable_inwait,
-};
-
-static struct clk emi_intr_clk = {
-	.name = "emi_intr_clk",
-	.parent = &ahb_clk,
-	.secondary = &ahbmux2_clk,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG9_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable_inwait,
-};
-
-static void _clk_ipg_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-	       MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static struct clk ipg_clk = {
-	.name = "ipg_clk",
-	.parent = &ahb_clk,
-	.recalc = _clk_ipg_recalc,
-	.flags = RATE_PROPAGATES,
-};
-
-static void _clk_ipg_per_recalc(struct clk *clk)
-{
-	u32 reg, prediv1, prediv2, podf;
-
-	if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
-		/* the main_bus_clk is the one before the DVFS engine */
-		reg = __raw_readl(MXC_CCM_CBCDR);
-		prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-			   MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
-		prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-			   MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
-		podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-			MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
-		clk->rate = clk->parent->rate / (prediv1 * prediv2 * podf);
-	} else if (clk->parent == &ipg_clk) {
-		clk->rate = ipg_clk.rate;
-	} else {
-		BUG();
-	}
-}
-
-static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL);
-	if (mux == 2) {
-		reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-	} else {
-		reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-		if (mux == 0)
-			reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-		else
-			reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-	}
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-static struct clk ipg_perclk = {
-	.name = "ipg_perclk",
-	.parent = &lp_apm_clk,
-	.recalc = _clk_ipg_per_recalc,
-	.set_parent = _clk_ipg_per_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_ipmux_enable(struct clk *clk)
-{
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg |= 1  << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
-
-	return 0;
-}
-
-static void _clk_ipmux_disable(struct clk *clk)
-{
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(0x1 << clk->enable_shift);
-	__raw_writel(reg, clk->enable_reg);
-}
-
-static struct clk ipumux1_clk = {
-	.name = "ipumux1",
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG6_1_OFFSET,
-	.enable = _clk_ipmux_enable,
-	.disable = _clk_ipmux_disable,
-};
-
-static struct clk ipumux2_clk = {
-	.name = "ipumux2",
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG6_2_OFFSET,
-	.enable = _clk_ipmux_enable,
-	.disable = _clk_ipmux_disable,
-};
-
-
-static struct clk aips_tz1_clk = {
-	.name = "aips_tz1_clk",
-	.parent = &ahb_clk,
-	.secondary = &ahb_max_clk,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG12_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable_inwait,
-};
-
-static struct clk aips_tz2_clk = {
-	.name = "aips_tz2_clk",
-	.parent = &ahb_clk,
-	.secondary = &ahb_max_clk,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG13_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable_inwait,
-};
-
-static struct clk gpc_dvfs_clk = {
-	.name = "gpc_dvfs_clk",
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG12_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-};
-
-static int _clk_sdma_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-
-	/* Handshake with SDMA when LPM is entered. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	return 0;
-}
-
-static void _clk_sdma_disable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_disable(clk);
-	/* No handshake with SDMA as its not enabled. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-
-static struct clk sdma_clk[] = {
-	{
-	 .name = "sdma_ahb_clk",
-	 .parent = &ahb_clk,
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG15_OFFSET,
-	 .enable = _clk_sdma_enable,
-	 .disable = _clk_sdma_disable,
-	 },
-	{
-	 .name = "sdma_ipg_clk",
-	 .parent = &ipg_clk,
-#ifdef CONFIG_SDMA_IRAM
-	 .secondary = &emi_intr_clk,
-#endif
-	 },
-};
-
-static int _clk_ipu_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-	/* Handshake with IPU when certain clock rates are changed. */
-	reg = __raw_readl(MXC_CCM_CCDR);
-	reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
-	__raw_writel(reg, MXC_CCM_CCDR);
-
-	/* Handshake with IPU when LPM is entered as its enabled. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	start_sdram_autogating();
-
-	return 0;
-}
-
-static void _clk_ipu_disable(struct clk *clk)
-{
-	u32 reg;
-
-	if (sdram_autogating_active())
-		stop_sdram_autogating();
-
-	_clk_disable(clk);
-
-	/* No handshake with IPU whe dividers are changed
-	 * as its not enabled. */
-	reg = __raw_readl(MXC_CCM_CCDR);
-	reg |= MXC_CCM_CCDR_IPU_HS_MASK;
-	__raw_writel(reg, MXC_CCM_CCDR);
-
-	/* No handshake with IPU when LPM is entered as its not enabled. */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &ahb_clk,
-		       &emi_slow_clk);
-	reg = (reg & ~MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-
-static struct clk ipu_clk[] = {
-	{
-	.name = "ipu_clk",
-	.parent = &ahb_clk,
-	.secondary = &ipu_clk[1],
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
-	.enable = _clk_ipu_enable,
-	.disable = _clk_ipu_disable,
-	.set_parent = _clk_ipu_set_parent,
-	 .flags = CPU_FREQ_TRIG_UPDATE | AHB_MED_SET_POINT | RATE_PROPAGATES,
-	},
-	{
-	 .name = "ipu_sec_clk",
-	 .parent = &emi_fast_clk,
-	 .secondary = &ahbmux1_clk,
-	}
-};
-
-static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	reg &= ~MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id);
-	if (parent == &pll3_sw_clk)
-		;
-	else if (parent == &osc_clk)
-		reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
-	else if (parent == &ckih_clk)
-		reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
-	else if (parent == &tve_clk)
-		reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
-	else		/* Assume any other clock is external clock pin */
-		reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_ipu_di_recalc(struct clk *clk)
-{
-	u32 reg, div, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	mux = (reg & MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id)) >>
-		MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
-	if (mux == 0) {
-		reg = __raw_readl(MXC_CCM_CDCDR) &
-		    MXC_CCM_CDCDR_DI_CLK_PRED_MASK;
-		div = (reg >> MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET) + 1;
-		clk->rate = clk->parent->rate / div;
-	} else if (mux == 3) {
-		clk->rate = clk->parent->rate / 8;
-	} else {
-		clk->rate = clk->parent->rate;
-	}
-}
-
-static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-
-	reg = __raw_readl(MXC_CCM_CDCDR);
-	reg &= ~MXC_CCM_CDCDR_DI_CLK_PRED_MASK;
-	reg |= (div - 1) << MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CDCDR);
-
-	clk->rate = rate;
-
-	return 0;
-}
-
-static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
-					    unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-static struct clk ipu_di_clk[] = {
-	{
-	.name = "ipu_di0_clk",
-	.id = 0,
-	.parent = &pll3_sw_clk,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG5_OFFSET,
-	.recalc = _clk_ipu_di_recalc,
-	.set_parent = _clk_ipu_di_set_parent,
-	.round_rate = _clk_ipu_di_round_rate,
-	.set_rate = _clk_ipu_di_set_rate,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-	.flags = RATE_PROPAGATES,
-	},
-	{
-	.name = "ipu_di1_clk",
-	.id = 1,
-	.parent = &pll3_sw_clk,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG6_OFFSET,
-	.recalc = _clk_ipu_di_recalc,
-	.set_parent = _clk_ipu_di_set_parent,
-	.round_rate = _clk_ipu_di_round_rate,
-	.set_rate = _clk_ipu_di_set_rate,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-	.flags = RATE_PROPAGATES,
-	},
-};
-
-static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
-	reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_csi0_recalc(struct clk *clk)
-{
-	u32 reg, pred, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR4);
-	pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK) >>
-			MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK) >>
-			MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / (pred * podf);
-}
-
-static unsigned long _clk_csi0_round_rate(struct clk *clk, unsigned long rate)
-{
-	u32 pre, post;
-	u32 div = clk->parent->rate / rate;
-	if (clk->parent->rate % rate)
-		div++;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	return clk->parent->rate / (pre * post);
-}
-
-static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg;
-	u32 div;
-	u32 pre, post;
-
-	div = clk->parent->rate / rate;
-
-	if ((clk->parent->rate / div) != rate)
-		return -EINVAL;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	/* Set CSI clock divider */
-	reg = __raw_readl(MXC_CCM_CSCDR4) &
-	    ~(MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK |
-		MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK);
-	reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET;
-	reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCDR4);
-
-	clk->rate = rate;
-	return 0;
-}
-
-static struct clk csi0_clk = {
-	.name = "csi_mclk1",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_csi0_set_parent,
-	.recalc = _clk_csi0_recalc,
-	.round_rate = _clk_csi0_round_rate,
-	.set_rate = _clk_csi0_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG2_OFFSET,
-	.disable = _clk_disable,
-};
-
-static int _clk_csi1_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
-	reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_csi1_recalc(struct clk *clk)
-{
-	u32 reg, pred, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR4);
-	pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK) >>
-			MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK) >>
-			MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / (pred * podf);
-}
-
-static unsigned long _clk_csi1_round_rate(struct clk *clk, unsigned long rate)
-{
-	u32 pre, post;
-	u32 div = clk->parent->rate / rate;
-	if (clk->parent->rate % rate)
-		div++;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	return clk->parent->rate / (pre * post);
-}
-
-static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg;
-	u32 div;
-	u32 pre, post;
-
-	div = clk->parent->rate / rate;
-
-	if ((clk->parent->rate / div) != rate)
-		return -EINVAL;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	/* Set CSI clock divider */
-	reg = __raw_readl(MXC_CCM_CSCDR4) &
-	    ~(MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK |
-		MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK);
-	reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET;
-	reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCDR4);
-
-	clk->rate = rate;
-	return 0;
-}
-
-static struct clk csi1_clk = {
-	.name = "csi_mclk2",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_csi1_set_parent,
-	.recalc = _clk_csi1_recalc,
-	.round_rate = _clk_csi1_round_rate,
-	.set_rate = _clk_csi1_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG3_OFFSET,
-	.disable = _clk_disable,
-};
-
-
-static int _clk_hsc_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-	/* Handshake with IPU when certain clock rates are changed. */
-	reg = __raw_readl(MXC_CCM_CCDR);
-	reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
-	__raw_writel(reg, MXC_CCM_CCDR);
-
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	return 0;
-}
-
-static void _clk_hsc_disable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_disable(clk);
-	/* No handshake with HSC as its not enabled. */
-	reg = __raw_readl(MXC_CCM_CCDR);
-	reg |= MXC_CCM_CCDR_HSC_HS_MASK;
-	__raw_writel(reg, MXC_CCM_CCDR);
-
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk mipi_esc_clk = {
-	.name = "mipi_esc_clk",
-	.parent = &pll2_sw_clk,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG5_OFFSET,
-};
-
-static struct clk mipi_hsc2_clk = {
-	.name = "mipi_hsc2_clk",
-	.parent = &pll2_sw_clk,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG4_OFFSET,
-	.secondary = &mipi_esc_clk,
-};
-
-static struct clk mipi_hsc1_clk = {
-	.name = "mipi_hsc1_clk",
-	.parent = &pll2_sw_clk,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG3_OFFSET,
-	.secondary = &mipi_hsc2_clk,
-};
-
-static struct clk mipi_hsp_clk = {
-	.name = "mipi_hsp_clk",
-	.parent = &ipu_clk[0],
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG6_OFFSET,
-	.enable = _clk_hsc_enable,
-	.disable = _clk_hsc_disable,
-	.secondary = &mipi_hsc1_clk,
-};
-
-static int _clk_tve_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-
-	if (parent == &pll3_sw_clk) {
-		reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL);
-	} else if (parent == &osc_clk) {
-		reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL;
-		reg &= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
-	} else if (parent == &ckih_clk) {
-		reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL;
-		reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
-	} else {
-		BUG();
-	}
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-	return 0;
-}
-
-static void _clk_tve_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if ((reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) == 0) {
-		reg = __raw_readl(MXC_CCM_CDCDR) &
-		    MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
-		div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1;
-		clk->rate = clk->parent->rate / div;
-	} else {
-		clk->rate = clk->parent->rate;
-	}
-}
-
-static unsigned long _clk_tve_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)
-		return -EINVAL;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-static int _clk_tve_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)
-		return -EINVAL;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-
-	div--;
-	reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
-	reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CDCDR);
-	clk->rate = rate;
-	return 0;
-}
-
-static int _clk_tve_enable(struct clk *clk)
-{
-	_clk_enable(clk);
-	if (clk_get_parent(&ipu_di_clk[1]) != clk) {
-		clk_enable(&ipu_di_clk[1]);
-		ipu_di_clk[1].set_parent(&ipu_di_clk[1], clk);
-		ipu_di_clk[1].parent = clk;
-	}
-	return 0;
-}
-
-static void _clk_tve_disable(struct clk *clk)
-{
-	_clk_disable(clk);
-	if (clk_get_parent(&ipu_di_clk[1]) == clk) {
-		ipu_di_clk[1].set_parent(&ipu_di_clk[1], &pll3_sw_clk);
-		ipu_di_clk[1].parent = &pll3_sw_clk;
-		clk_disable(&ipu_di_clk[1]);
-	}
-}
-
-static struct clk tve_clk = {
-	.name = "tve_clk",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_tve_set_parent,
-	.enable_reg = MXC_CCM_CCGR2,
-	.enable_shift = MXC_CCM_CCGR2_CG15_OFFSET,
-	.recalc = _clk_tve_recalc,
-	.round_rate = _clk_tve_round_rate,
-	.set_rate = _clk_tve_set_rate,
-	.enable = _clk_tve_enable,
-	.disable = _clk_tve_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
-static struct clk spba_clk = {
-	.name = "spba_clk",
-	.parent = &ipg_clk,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG0_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-};
-
-static void _clk_uart_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-		       &lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk uart_main_clk = {
-	.name = "uart_main_clk",
-	.parent = &pll2_sw_clk,
-	.recalc = _clk_uart_recalc,
-	.set_parent = _clk_uart_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk uart1_clk[] = {
-	{
-	 .name = "uart_clk",
-	 .id = 0,
-	 .parent = &uart_main_clk,
-	 .secondary = &uart1_clk[1],
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG4_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-#ifdef UART1_DMA_ENABLE
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-#endif
-	 },
-	{
-	 .name = "uart_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-#ifdef UART1_DMA_ENABLE
-	 .secondary = &aips_tz1_clk,
-#endif
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG3_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-};
-
-static struct clk uart2_clk[] = {
-	{
-	 .name = "uart_clk",
-	 .id = 1,
-	 .parent = &uart_main_clk,
-	 .secondary = &uart2_clk[1],
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG6_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-#ifdef UART2_DMA_ENABLE
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-#endif
-	 },
-	{
-	 .name = "uart_ipg_clk",
-	 .id = 1,
-	 .parent = &ipg_clk,
-#ifdef UART2_DMA_ENABLE
-	 .secondary = &aips_tz1_clk,
-#endif
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG5_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-};
-
-static struct clk uart3_clk[] = {
-	{
-	 .name = "uart_clk",
-	 .id = 2,
-	 .parent = &uart_main_clk,
-	 .secondary = &uart3_clk[1],
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG8_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-#ifdef UART3_DMA_ENABLE
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-#endif
-	 },
-	{
-	 .name = "uart_ipg_clk",
-	 .id = 2,
-	 .parent = &ipg_clk,
-	 .secondary = &spba_clk,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG7_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-};
-
-static struct clk gpt_clk[] = {
-	{
-	 .name = "gpt_clk",
-	 .parent = &ipg_perclk,
-	 .id = 0,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 .secondary = &gpt_clk[1],
-	 },
-	{
-	 .name = "gpt_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "gpt_32k_clk",
-	 .id = 0,
-	 .parent = &ckil_clk,
-	 },
-};
-
-static struct clk pwm1_clk[] = {
-	{
-	 .name = "pwm",
-	 .parent = &ipg_perclk,
-	 .id = 0,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG6_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 .secondary = &pwm1_clk[1],
-	 },
-	{
-	 .name = "pwm_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG5_OFFSET,
-	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "pwm_32k_clk",
-	 .id = 0,
-	 .parent = &ckil_clk,
-	 },
-};
-
-static struct clk pwm2_clk[] = {
-	{
-	 .name = "pwm",
-	 .parent = &ipg_perclk,
-	 .id = 1,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG8_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 .secondary = &pwm2_clk[1],
-	 },
-	{
-	 .name = "pwm_ipg_clk",
-	 .id = 1,
-	 .parent = &ipg_clk,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG7_OFFSET,
-	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "pwm_32k_clk",
-	 .id = 1,
-	 .parent = &ckil_clk,
-	 },
-};
-
-static struct clk i2c_clk[] = {
-	{
-	 .name = "i2c_clk",
-	 .id = 0,
-	 .parent = &ipg_perclk,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG9_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "i2c_clk",
-	 .id = 1,
-	 .parent = &ipg_perclk,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-};
-
-static void _clk_hsi2c_serial_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR3);
-	prediv = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static struct clk hsi2c_serial_clk = {
-	.name = "hsi2c_serial_clk",
-	.id = 0,
-	.parent = &pll3_sw_clk,
-	.secondary = &spba_clk,
-	.enable_reg = MXC_CCM_CCGR1,
-	.enable_shift = MXC_CCM_CCGR1_CG11_OFFSET,
-	.recalc = _clk_hsi2c_serial_recalc,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-};
-
-static struct clk hsi2c_clk = {
-	.name = "hsi2c_clk",
-	.id = 0,
-	.parent = &ipg_clk,
-	.enable_reg = MXC_CCM_CCGR1,
-	.enable_shift = MXC_CCM_CCGR1_CG12_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
-static void _clk_cspi_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR2);
-	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
-	if (prediv == 1)
-		BUG();
-	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-		       &lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk cspi_main_clk = {
-	.name = "cspi_main_clk",
-	.parent = &pll3_sw_clk,
-	.recalc = _clk_cspi_recalc,
-	.set_parent = _clk_cspi_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-static struct clk cspi1_clk[] = {
-	{
-	 .name = "cspi_clk",
-	 .id = 0,
-	 .parent = &cspi_main_clk,
-	 .secondary = &cspi1_clk[1],
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG10_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "cspi_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .secondary = &spba_clk,
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG9_OFFSET,
-	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
-	 .disable = _clk_disable,
-	 },
-};
-
-static struct clk cspi2_clk[] = {
-	{
-	 .name = "cspi_clk",
-	 .id = 1,
-	 .parent = &cspi_main_clk,
-	 .secondary = &cspi2_clk[1],
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG12_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "cspi_ipg_clk",
-	 .id = 1,
-	 .parent = &ipg_clk,
-	 .secondary = &aips_tz2_clk,
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG11_OFFSET,
-	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
-	 .disable = _clk_disable,
-	 },
-};
-
-static struct clk cspi3_clk[] = {
-	{
-	 .name = "cspi_clk",
-	 .id = 2,
-	 .parent = &cspi_main_clk,
-	 .enable_reg = MXC_CCM_CCGR4,
-	 .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 .secondary = &cspi3_clk[1],
-	 },
-	{
-	 .name = "cspi_ipg_clk",
-	 .id = 2,
-	 .parent = &ipg_clk,
-	 .secondary = &aips_tz2_clk,
-	 },
-};
-
-static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL);
-	reg = __raw_readl(MXC_CCM_CSCMR1) &
-	    ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk ssi_lp_apm_clk = {
-	.name = "ssi_lp_apm_clk",
-	.parent = &ckih_clk,
-	.set_parent = _clk_ssi_lp_apm_set_parent,
-};
-
-static void _clk_ssi1_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CS1CDR);
-	prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >>
-		  MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
-	if (prediv == 1)
-		BUG();
-	podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >>
-		MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
-		       &pll3_sw_clk, &ssi_lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk ssi1_clk[] = {
-	{
-	 .name = "ssi_clk",
-	 .id = 0,
-	 .parent = &pll3_sw_clk,
-	 .set_parent = _clk_ssi1_set_parent,
-	 .secondary = &ssi1_clk[1],
-	 .recalc = _clk_ssi1_recalc,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG9_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "ssi_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .secondary = &ssi1_clk[2],
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG8_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "ssi_dep_clk",
-	 .id = 0,
-	 .parent = &aips_tz2_clk,
-#ifdef CONFIG_SND_MXC_SOC_IRAM
-	 .secondary = &emi_intr_clk,
-#else
-	 .secondary = &emi_fast_clk,
-#endif
-	 },
-};
-
-static void _clk_ssi2_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CS2CDR);
-	prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >>
-		  MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
-	if (prediv == 1)
-		BUG();
-	podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >>
-		MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
-		       &pll3_sw_clk, &ssi_lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk ssi2_clk[] = {
-	{
-	 .name = "ssi_clk",
-	 .id = 1,
-	 .parent = &pll3_sw_clk,
-	 .set_parent = _clk_ssi2_set_parent,
-	 .secondary = &ssi2_clk[1],
-	 .recalc = _clk_ssi2_recalc,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG11_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "ssi_ipg_clk",
-	 .id = 1,
-	 .parent = &ipg_clk,
-	 .secondary = &ssi2_clk[2],
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG10_OFFSET,
-	 .enable = _clk_enable,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "ssi_dep_clk",
-	 .id = 1,
-	 .parent = &spba_clk,
-#ifdef CONFIG_SND_MXC_SOC_IRAM
-	 .secondary = &emi_intr_clk,
-#else
-	 .secondary = &emi_fast_clk,
-#endif
-	 },
-};
-
-static void _clk_ssi_ext1_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	clk->rate = clk->parent->rate;
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) {
-		reg = __raw_readl(MXC_CCM_CS1CDR);
-		prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >>
-			  MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1;
-		if (prediv == 1)
-			BUG();
-		podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >>
-			MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1;
-		clk->rate = clk->parent->rate / (prediv * podf);
-	}
-}
-
-static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (parent == &ssi1_clk[0]) {
-		reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
-	} else {
-		reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
-		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-			       &ssi_lp_apm_clk);
-		reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET);
-	}
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk ssi_ext1_clk = {
-	.name = "ssi_ext1_clk",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_ssi_ext1_set_parent,
-	.recalc = _clk_ssi_ext1_recalc,
-	.enable_reg = MXC_CCM_CCGR3,
-	.enable_shift = MXC_CCM_CCGR3_CG14_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-};
-
-static void _clk_ssi_ext2_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	clk->rate = clk->parent->rate;
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) {
-		reg = __raw_readl(MXC_CCM_CS2CDR);
-		prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >>
-			  MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1;
-		if (prediv == 1)
-			BUG();
-		podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >>
-			MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1;
-		clk->rate = clk->parent->rate / (prediv * podf);
-	}
-}
-
-static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (parent == &ssi2_clk[0]) {
-		reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
-	} else {
-		reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
-		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-			       &ssi_lp_apm_clk);
-		reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET);
-	}
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk ssi_ext2_clk = {
-	.name = "ssi_ext2_clk",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_ssi_ext2_set_parent,
-	.recalc = _clk_ssi_ext2_recalc,
-	.enable_reg = MXC_CCM_CCGR3,
-	.enable_shift = MXC_CCM_CCGR3_CG15_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-};
-
-static struct clk iim_clk = {
-	.name = "iim_clk",
-	.parent = &ipg_clk,
-	.secondary = &aips_tz2_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG15_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk tmax1_clk = {
-	 .name = "tmax1_clk",
-	 .id = 0,
-	 .parent = &ahb_clk,
-	 .secondary = &ahb_max_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG0_OFFSET,
-	 .disable = _clk_disable,
-	 };
-
-static struct clk tmax2_clk = {
-	 .name = "tmax2_clk",
-	 .id = 0,
-	 .parent = &ahb_clk,
-	 .secondary = &ahb_max_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG1_OFFSET,
-	 .disable = _clk_disable,
-};
-
-static struct clk tmax3_clk = {
-	 .name = "tmax3_clk",
-	 .id = 0,
-	 .parent = &ahb_clk,
-	 .secondary = &ahb_max_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR1,
-	 .enable_shift = MXC_CCM_CCGR1_CG2_OFFSET,
-	 .disable = _clk_disable,
-};
-
-static void _clk_usboh3_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
-	if (prediv == 1)
-		BUG();
-	podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-		       &lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk usboh3_clk[] = {
-	{
-	 .name = "usboh3_clk",
-	 .parent = &pll3_sw_clk,
-	 .set_parent = _clk_usboh3_set_parent,
-	 .recalc = _clk_usboh3_recalc,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG14_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &usboh3_clk[1],
-	 .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	 },
-	{
-	 .name = "usb_sec_clk",
-	 .parent = &tmax2_clk,
-#if defined(CONFIG_USB_STATIC_IRAM) \
-    || defined(CONFIG_USB_STATIC_IRAM_PPH)
-	 .secondary = &emi_intr_clk,
-#else
-	 .secondary = &emi_fast_clk,
-#endif
-	 },
-};
-static struct clk usb_ahb_clk = {
-	 .name = "usb_ahb_clk",
-	 .parent = &ipg_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET,
-	 .disable = _clk_disable,
-};
-
-static void _clk_usb_phy_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	if (clk->parent == &pll3_sw_clk) {
-		reg = __raw_readl(MXC_CCM_CDCDR);
-		prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >>
-			  MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1;
-		podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >>
-			MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1;
-
-		clk->rate = clk->parent->rate / (prediv * podf);
-	} else
-		clk->rate = clk->parent->rate;
-}
-
-static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (parent == &osc_clk)
-		reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	else if (parent == &pll3_sw_clk)
-		reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	else
-		BUG();
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-	return 0;
-}
-
-static struct clk usb_phy_clk = {
-	.name = "usb_phy_clk",
-	.parent = &pll3_sw_clk,
-	.secondary = &tmax3_clk,
-	.set_parent = _clk_usb_phy_set_parent,
-	.recalc = _clk_usb_phy_recalc,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR2,
-	.enable_shift = MXC_CCM_CCGR2_CG0_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk esdhc_dep_clks = {
-	 .name = "sd_dep_clk",
-	 .parent = &spba_clk,
-	 .secondary = &emi_fast_clk,
-};
-
-
-static void _clk_esdhc1_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-		       &lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) &
-	    ~MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk esdhc1_clk[] = {
-	{
-	 .name = "esdhc_clk",
-	 .id = 0,
-	 .parent = &pll3_sw_clk,
-	 .set_parent = _clk_esdhc1_set_parent,
-	 .recalc = _clk_esdhc1_recalc,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &esdhc1_clk[1],
-	 },
-	{
-	 .name = "esdhc_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .secondary = &esdhc1_clk[2],
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG0_OFFSET,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "esdhc_sec_clk",
-	 .id = 0,
-	 .parent = &tmax3_clk,
-	 .secondary = &esdhc_dep_clks,
-	 },
-
-};
-
-static void _clk_esdhc2_recalc(struct clk *clk)
-{
-	u32 reg, prediv, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >>
-		  MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1;
-
-	clk->rate = clk->parent->rate / (prediv * podf);
-}
-
-static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-		       &lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CSCMR1) &
-	    ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk esdhc2_clk[] = {
-	{
-	 .name = "esdhc_clk",
-	 .id = 1,
-	 .parent = &pll3_sw_clk,
-	 .set_parent = _clk_esdhc2_set_parent,
-	 .recalc = _clk_esdhc2_recalc,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &esdhc2_clk[1],
-	 },
-	{
-	 .name = "esdhc_ipg_clk",
-	 .id = 1,
-	 .parent = &ipg_clk,
-	 .secondary = &esdhc2_clk[2],
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG2_OFFSET,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "esdhc_sec_clk",
-	 .id = 0,
-	 .parent = &tmax2_clk,
-	 .secondary = &esdhc_dep_clks,
-	 },
-};
-
-static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (parent == &esdhc1_clk[0])
-		reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-	else if (parent == &esdhc2_clk[0])
-		reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-	else
-		BUG();
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk esdhc3_clk[] = {
-	{
-	 .name = "esdhc_clk",
-	 .id = 2,
-	 .parent = &esdhc1_clk[0],
-	 .set_parent = _clk_esdhc3_set_parent,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &esdhc3_clk[1],
-	 },
-	{
-	 .name = "esdhc_ipg_clk",
-	 .id = 2,
-	 .parent = &ipg_clk,
-	 .secondary = &esdhc3_clk[2],
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG4_OFFSET,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "esdhc_sec_clk",
-	 .id = 0,
-	 .parent = &ahb_max_clk,
-	 .secondary = &esdhc_dep_clks,
-	 },
-};
-
-
-static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CSCMR1);
-	if (parent == &esdhc1_clk[0])
-		reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-	else if (parent == &esdhc2_clk[0])
-		reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-	else
-		BUG();
-
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk esdhc4_clk[] = {
-	{
-	 .name = "esdhc_clk",
-	 .id = 3,
-	 .parent = &esdhc1_clk[0],
-	 .set_parent = _clk_esdhc4_set_parent,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &esdhc4_clk[1],
-	 },
-	{
-	 .name = "esdhc_ipg_clk",
-	 .id = 3,
-	 .parent = &ipg_clk,
-	 .secondary = &esdhc4_clk[2],
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR3,
-	 .enable_shift = MXC_CCM_CCGR3_CG6_OFFSET,
-	 .disable = _clk_disable,
-	 },
-	{
-	 .name = "esdhc_sec_clk",
-	 .id = 0,
-	 .parent = &tmax3_clk,
-	 .secondary = &esdhc_dep_clks,
-	 },
-};
-
-static int _clk_sim_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
-	reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_sim_recalc(struct clk *clk)
-{
-	u32 reg, pred, podf;
-
-	reg = __raw_readl(MXC_CCM_CSCDR2);
-	pred = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / (pred * podf);
-}
-
-static unsigned long _clk_sim_round_rate(struct clk *clk, unsigned long rate)
-{
-	u32 pre, post;
-	u32 div = clk->parent->rate / rate;
-	if (clk->parent->rate % rate)
-		div++;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	return clk->parent->rate / (pre * post);
-}
-
-static int _clk_sim_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg;
-	u32 div;
-	u32 pre, post;
-
-	div = clk->parent->rate / rate;
-
-	if ((clk->parent->rate / div) != rate)
-		return -EINVAL;
-
-	__calc_pre_post_dividers(div, &pre, &post);
-
-	/* Set SIM clock divider */
-	reg = __raw_readl(MXC_CCM_CSCDR2) &
-	    ~(MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK |
-	      MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK);
-	reg |= (post - 1) << MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET;
-	reg |= (pre - 1) << MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCDR2);
-
-	clk->rate = rate;
-	return 0;
-
-}
-
-static struct clk sim_clk[] = {
-	{
-	.name = "sim_clk",
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_sim_set_parent,
-	.secondary = &sim_clk[1],
-	.recalc = _clk_sim_recalc,
-	.round_rate = _clk_sim_round_rate,
-	.set_rate = _clk_sim_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG2_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	 },
-	{
-	.name = "sim_ipg_clk",
-	.parent = &ipg_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG1_OFFSET,
-	.disable = _clk_disable,
-	 },
-};
-
-static void _clk_nfc_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
-	       MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static unsigned long _clk_nfc_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	u32 div;
-
-	/*
-	 * Compute the divider we'd have to use to reach the target rate.
-	 */
-
-	div = clk->parent->rate / rate;
-
-	/*
-	 * If there's a remainder after the division, then we have to increment
-	 * the divider. There are two reasons for this:
-	 *
-	 * 1) The frequency we round to must be LESS THAN OR EQUAL to the
-	 *    target. We aren't allowed to round to a frequency that is higher
-	 *    than the target.
-	 *
-	 * 2) This also catches the case where target rate is less than the
-	 *    parent rate, which implies a divider of zero. We can't allow a
-	 *    divider of zero.
-	 */
-
-	if (clk->parent->rate % rate)
-		div++;
-
-	/*
-	 * The divider for this clock is 3 bits wide, so we can't possibly
-	 * divide the parent by more than eight.
-	 */
-
-	if (div > 8)
-		return -EINVAL;
-
-	return clk->parent->rate / div;
-
-}
-
-static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.enable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.enable(&emi_slow_clk);
-
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) &
-			MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
-		getnstimeofday(&curtime);
-		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
-			panic("_clk_nfc_set_rate failed\n");
-	}
-	clk->rate = rate;
-	if (emi_fast_clk.usecount == 0)
-		emi_fast_clk.disable(&emi_fast_clk);
-	if (emi_slow_clk.usecount == 0)
-		emi_slow_clk.disable(&emi_slow_clk);
-
-	return 0;
-}
-
-static struct clk emi_enfc_clk = {
-	.name = "nfc_clk",
-	.parent = &emi_slow_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG10_OFFSET,
-	.disable = _clk_disable_inwait,
-	.recalc = _clk_nfc_recalc,
-	.round_rate = _clk_nfc_round_rate,
-	.set_rate = _clk_nfc_set_rate,
-};
-
-static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	mux = _get_mux(parent, &osc_clk, &ckih_clk, &ckih2_clk, NULL);
-	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK;
-	reg |= mux << MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCMR1);
-
-	return 0;
-}
-
-static struct clk spdif_xtal_clk = {
-	.name = "spdif_xtal_clk",
-	.parent = &osc_clk,
-	.set_parent = _clk_spdif_xtal_set_parent,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG15_OFFSET,
-	.disable = _clk_disable,
-};
-
-static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	reg |= MXC_CCM_CSCMR2_SPDIF0_COM;
-	if (parent != &ssi1_clk[0]) {
-		reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM;
-		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-			       &spdif_xtal_clk);
-		reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET);
-	}
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_spdif0_recalc(struct clk *clk)
-{
-	u32 reg, pred, podf;
-
-	if (clk->parent == &ssi1_clk[0]) {
-		clk->rate = clk->parent->rate;
-	} else {
-		reg = __raw_readl(MXC_CCM_CDCDR);
-		pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >>
-			MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
-		podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >>
-			MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
-		clk->rate = clk->parent->rate / (pred * podf);
-	}
-}
-
-static struct clk spdif0_clk[] = {
-	{
-	.name = "spdif_clk",
-	.id = 0,
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_spdif0_set_parent,
-	.recalc = _clk_spdif0_recalc,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG13_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	},
-	{
-	 .name = "spdif_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .secondary = &spba_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR5,
-	 .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET,
-	 .disable = _clk_disable,
-	 },
-};
-
-static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CSCMR2);
-	reg |= MXC_CCM_CSCMR2_SPDIF1_COM;
-	if (parent != &ssi2_clk[0]) {
-		reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM;
-		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-			       &spdif_xtal_clk);
-		reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET);
-	}
-	__raw_writel(reg, MXC_CCM_CSCMR2);
-
-	return 0;
-}
-
-static void _clk_spdif1_recalc(struct clk *clk)
-{
-	u32 reg, pred, podf;
-
-	if (clk->parent == &ssi2_clk[0]) {
-		clk->rate = clk->parent->rate;
-	} else {
-		reg = __raw_readl(MXC_CCM_CDCDR);
-		pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >>
-			MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
-		podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >>
-			MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
-		clk->rate = clk->parent->rate / (pred * podf);
-	}
-}
-
-static struct clk spdif1_clk[] = {
-	{
-	.name = "spdif_clk",
-	.id = 1,
-	.parent = &pll3_sw_clk,
-	.set_parent = _clk_spdif1_set_parent,
-	.recalc = _clk_spdif1_recalc,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG14_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	},
-	{
-	 .name = "spdif_ipg_clk",
-	 .id = 0,
-	 .parent = &ipg_clk,
-	 .secondary = &spba_clk,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR5,
-	 .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET,
-	 .disable = _clk_disable,
-	 },
-};
-
-static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, reg2, mux;
-	struct timespec nstimeofday;
-	struct timespec curtime;
-
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	reg2 = __raw_readl(MXC_CCM_CBCDR);
-	mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk);
-	if (mux < 4) {
-		reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) |
-		    (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET);
-		__raw_writel(reg, MXC_CCM_CBCMR);
-		reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL);
-	} else {
-		reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) |
-			(MXC_CCM_CBCDR_DDR_HF_SEL);
-	}
-	__raw_writel(reg2, MXC_CCM_CBCDR);
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) &
-		MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){
-		getnstimeofday(&curtime);
-		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
-			panic("_clk_ddr_set_parent failed\n");
-	}
-	return 0;
-}
-
-static struct clk ddr_clk = {
-	.name = "ddr_clk",
-	.parent = &ddr_hf_clk,
-	.set_parent = _clk_ddr_set_parent,
-	.flags = RATE_PROPAGATES,
-};
-
-static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
-	reg = (reg & ~MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-static struct clk arm_axi_clk = {
-	.name = "arm_axi_clk",
-	.parent = &axi_a_clk,
-	.set_parent = _clk_arm_axi_set_parent,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR0,
-	.enable_shift = MXC_CCM_CCGR0_CG1_OFFSET,
-	.disable = _clk_disable,
-};
-
-static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
-	reg = (reg & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-static int _clk_vpu_enable(struct clk *clk)
-{
-	/* Set VPU's parent to be axi_a or ahb when its enabled. */
-	if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) {
-		clk_set_parent(&vpu_clk[0], &ahb_clk);
-		clk_set_parent(&vpu_clk[1], &ahb_clk);
-	} else {
-		clk_set_parent(&vpu_clk[0], &axi_a_clk);
-		clk_set_parent(&vpu_clk[1], &axi_a_clk);
-	}
-
-	return _clk_enable(clk);
-
-}
-
-static void _clk_vpu_disable(struct clk *clk)
-{
-	_clk_disable(clk);
-
-	/* Set VPU's parent to be axi_b when its disabled. */
-	clk_set_parent(&vpu_clk[0], &axi_b_clk);
-	clk_set_parent(&vpu_clk[1], &axi_b_clk);
-}
-
-static struct clk vpu_clk[] = {
-	{
-	 .name = "vpu_clk",
-	 .set_parent = _clk_vpu_set_parent,
-	 .enable = _clk_enable,
-	 .enable_reg = MXC_CCM_CCGR5,
-	 .enable_shift = MXC_CCM_CCGR5_CG4_OFFSET,
-	 .disable = _clk_disable,
-	 .secondary = &vpu_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	 },
-	{
-	 .name = "vpu_core_clk",
-	 .set_parent = _clk_vpu_set_parent,
-	 .enable = _clk_vpu_enable,
-	 .enable_reg = MXC_CCM_CCGR5,
-	 .enable_shift = MXC_CCM_CCGR5_CG3_OFFSET,
-	 .disable = _clk_vpu_disable,
-	 .secondary = &vpu_clk[2],
-	 },
-	{
-	 .name = "vpu_emi_clk",
-	 .parent = &emi_fast_clk,
-#ifdef CONFIG_MXC_VPU_IRAM
-	 .secondary = &emi_intr_clk,
-#endif
-	 }
-};
-
-static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	mux = _get_mux(parent, &ckil_clk, &fpm_clk, &fpm_div2_clk, NULL);
-	reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	return 0;
-}
-
-static struct clk lpsr_clk = {
-	.name = "lpsr_clk",
-	.parent = &ckil_clk,
-	.set_parent = _clk_lpsr_set_parent,
-};
-
-static void _clk_pgc_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >>
-	    MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET;
-	div = 1 >> div;
-	clk->rate = clk->parent->rate / div;
-}
-
-static struct clk pgc_clk = {
-	.name = "pgc_clk",
-	.parent = &ipg_clk,
-	.recalc = _clk_pgc_recalc,
-};
-
-/*usb OTG clock */
-
-static struct clk usb_clk = {
-	.name = "usb_clk",
-	.rate = 60000000,
-};
-
-static struct clk usb_utmi_clk = {
-	.name = "usb_utmi_clk",
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CSCMR1,
-	.enable_shift = MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk rtc_clk = {
-	.name = "rtc_clk",
-	.parent = &ckil_clk,
-	.secondary = &ipg_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG14_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk ata_clk = {
-	.name = "ata_clk",
-	.parent = &ipg_clk,
-	.secondary = &spba_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG0_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
-static struct clk owire_clk = {
-	.name = "owire_clk",
-	.parent = &ipg_perclk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR2,
-	.enable_shift = MXC_CCM_CCGR2_CG11_OFFSET,
-	.disable = _clk_disable,
-};
-
-
-static struct clk fec_clk[] = {
-	{
-	.name = "fec_clk",
-	.parent = &ipg_clk,
-	.secondary = &fec_clk[1],
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR2,
-	.enable_shift = MXC_CCM_CCGR2_CG12_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-	},
-	{
-	 .name = "fec_sec1_clk",
-	 .parent = &tmax2_clk,
-	 .secondary = &fec_clk[2],
-	},
-	{
-	 .name = "fec_sec2_clk",
-	 .parent = &aips_tz2_clk,
-	 .secondary = &emi_fast_clk,
-	},
-};
-
-static struct clk sahara_clk[] = {
-	{
-	.name = "sahara_clk",
-	.parent = &ahb_clk,
-	.secondary = &sahara_clk[1],
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGR4_CG7_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-	},
-	{
-	.name = "sahara_sec_clk",
-	.parent = &tmax1_clk,
-	.secondary = &emi_fast_clk,
-	}
-};
-
-static struct clk scc_clk[] = {
-	{
-	.name = "scc_clk",
-	.parent = &ahb_clk,
-	.secondary = &scc_clk[1],
-	.enable_reg = MXC_CCM_CCGR1,
-	.enable_shift = MXC_CCM_CCGR1_CG15_OFFSET,
-	.enable = _clk_enable,
-	.disable = _clk_disable,
-	},
-	{
-	.name = "scc_sec_clk",
-	.parent = &tmax1_clk,
-	.secondary = &emi_fast_clk,
-	}
-};
-
-
-static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
-	reg = (reg & ~MXC_CCM_CBCMR_GPU_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-static struct clk gpu3d_clk = {
-	.name = "gpu3d_clk",
-	.parent = &axi_a_clk,
-	.set_parent = _clk_gpu3d_set_parent,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG1_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
-static struct clk garb_clk = {
-	.name = "garb_clk",
-	.parent = &axi_a_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG2_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk emi_garb_clk = {
-	.name = "emi_garb_clk",
-	.parent = &axi_a_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG4_OFFSET,
-	.disable = _clk_disable,
-};
-
-static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg, mux;
-
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
-	reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
-	    (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCMR);
-
-	return 0;
-}
-
-static struct clk gpu2d_clk = {
-	.name = "gpu2d_clk",
-	.parent = &axi_a_clk,
-	.set_parent = _clk_gpu2d_set_parent,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG7_OFFSET,
-	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
-static struct clk *mxc_clks[] = {
-	&osc_clk,
-	&ckih_clk,
-	&ckih2_clk,
-	&ckil_clk,
-	&fpm_clk,
-	&fpm_div2_clk,
-	&pll1_main_clk,
-	&pll1_sw_clk,
-	&pll2_sw_clk,
-	&pll3_sw_clk,
-	&ipumux1_clk,
-	&ipumux2_clk,
-	&gpc_dvfs_clk,
-	&lp_apm_clk,
-	&cpu_clk,
-	&periph_apm_clk,
-	&main_bus_clk,
-	&axi_a_clk,
-	&axi_b_clk,
-	&ahb_clk,
-	&ahb_max_clk,
-	&ipg_clk,
-	&ipg_perclk,
-	&ahbmux1_clk,
-	&ahbmux2_clk,
-	&aips_tz1_clk,
-	&aips_tz2_clk,
-	&sdma_clk[0],
-	&sdma_clk[1],
-	&ipu_clk[0],
-	&ipu_clk[1],
-	&ipu_di_clk[0],
-	&ipu_di_clk[1],
-	&tve_clk,
-	&csi0_clk,
-	&csi1_clk,
-	&uart_main_clk,
-	&uart1_clk[0],
-	&uart1_clk[1],
-	&uart2_clk[0],
-	&uart2_clk[1],
-	&uart3_clk[0],
-	&uart3_clk[1],
-	&spba_clk,
-	&i2c_clk[0],
-	&i2c_clk[1],
-	&hsi2c_clk,
-	&hsi2c_serial_clk,
-	&gpt_clk[0],
-	&gpt_clk[1],
-	&gpt_clk[2],
-	&pwm1_clk[0],
-	&pwm1_clk[1],
-	&pwm1_clk[2],
-	&pwm2_clk[0],
-	&pwm2_clk[1],
-	&pwm2_clk[2],
-	&cspi_main_clk,
-	&cspi1_clk[0],
-	&cspi1_clk[1],
-	&cspi2_clk[0],
-	&cspi2_clk[1],
-	&cspi3_clk[0],
-	&cspi3_clk[1],
-	&ssi_lp_apm_clk,
-	&ssi1_clk[0],
-	&ssi1_clk[1],
-	&ssi1_clk[2],
-	&ssi2_clk[0],
-	&ssi2_clk[1],
-	&ssi2_clk[2],
-	&ssi_ext1_clk,
-	&ssi_ext2_clk,
-	&iim_clk,
-	&tmax1_clk,
-	&tmax2_clk,
-	&tmax3_clk,
-	&usboh3_clk[0],
-	&usboh3_clk[1],
-	&usb_ahb_clk,
-	&usb_phy_clk,
-	&usb_utmi_clk,
-	&usb_clk,
-	&esdhc1_clk[0],
-	&esdhc1_clk[1],
-	&esdhc2_clk[0],
-	&esdhc2_clk[1],
-	&esdhc3_clk[0],
-	&esdhc3_clk[1],
-	&esdhc4_clk[0],
-	&esdhc4_clk[1],
-	&esdhc_dep_clks,
-	&sim_clk[0],
-	&sim_clk[1],
-	&emi_slow_clk,
-	&ddr_clk,
-	&emi_enfc_clk,
-	&emi_fast_clk,
-	&emi_intr_clk,
-	&spdif_xtal_clk,
-	&spdif0_clk[0],
-	&spdif0_clk[1],
-	&spdif1_clk[0],
-	&spdif1_clk[1],
-	&arm_axi_clk,
-	&vpu_clk[0],
-	&vpu_clk[1],
-	&vpu_clk[2],
-	&lpsr_clk,
-	&pgc_clk,
-	&rtc_clk,
-	&ata_clk,
-	&owire_clk,
-	&fec_clk[0],
-	&fec_clk[1],
-	&fec_clk[2],
-	&mipi_hsc1_clk,
-	&mipi_hsc2_clk,
-	&mipi_esc_clk,
-	&mipi_hsp_clk,
-	&sahara_clk[0],
-	&sahara_clk[1],
-	&gpu3d_clk,
-	&garb_clk,
-	&emi_garb_clk,
-	&ddr_hf_clk,
-	&gpu2d_clk,
-	&scc_clk[0],
-	&scc_clk[1],
-};
-
-static void clk_tree_init(void)
-{
-	u32 reg, reg2, dp_ctl;
-
-	ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
-
-	/*
-	 *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
-	 * 8MHz, its derived from lp_apm.
-	 */
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
-	reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
-	reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
-	reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	/* set pll1_main_clk parent */
-	pll1_main_clk.parent = &osc_clk;
-	dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
-	if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
-		pll1_main_clk.parent = &fpm_clk;
-	/* set pll2_sw_clk parent */
-	pll2_sw_clk.parent = &osc_clk;
-	dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL);
-	if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
-		pll2_sw_clk.parent = &fpm_clk;
-	/* set pll3_clk parent */
-	pll3_sw_clk.parent = &osc_clk;
-	dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL);
-	if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
-		pll3_sw_clk.parent = &fpm_clk;
-
-	/* set emi_slow_clk parent */
-	emi_slow_clk.parent = &main_bus_clk;
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	if ((reg & MXC_CCM_CBCDR_EMI_CLK_SEL) != 0)
-		emi_slow_clk.parent = &ahb_clk;
-
-	/* set ipg_perclk parent */
-	ipg_perclk.parent = &lp_apm_clk;
-	reg = __raw_readl(MXC_CCM_CBCMR);
-	if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) {
-		ipg_perclk.parent = &ipg_clk;
-	} else {
-		if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0)
-			ipg_perclk.parent = &main_bus_clk;
-	}
-
-	/* set DDR clock parent */
-	reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK;
-	reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
-	reg2 = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL;
-	reg2 >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET;
-
-	if (reg2) {
-		ddr_clk.parent = &ddr_hf_clk;
-	} else {
-		if (reg == 0) {
-			ddr_clk.parent = &axi_a_clk;
-		} else if (reg == 1) {
-			ddr_clk.parent = &axi_b_clk;
-		} else if (reg == 2) {
-			ddr_clk.parent = &emi_slow_clk;
-		} else {
-			ddr_clk.parent = &ahb_clk;
-		}
-	}
-}
-
-int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
-{
-	__iomem void *base;
-	struct clk **clkp;
-	int i = 0, j = 0, reg;
-	int wp_cnt = 0;
-
-	pll1_base = ioremap(PLL1_BASE_ADDR, SZ_4K);
-	pll2_base = ioremap(PLL2_BASE_ADDR, SZ_4K);
-	pll3_base = ioremap(PLL3_BASE_ADDR, SZ_4K);
-
-	/* Turn off all possible clocks */
-	if (mxc_jtag_enabled) {
-		__raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG1_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG2_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG3_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG4_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG8_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG9_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG12_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG13_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0);
-	} else {
-		__raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG1_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG2_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG3_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG8_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG9_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG12_OFFSET |
-			      1 << MXC_CCM_CCGR0_CG13_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0);
-	}
-	__raw_writel(0, MXC_CCM_CCGR1);
-	__raw_writel(0, MXC_CCM_CCGR2);
-	__raw_writel(0, MXC_CCM_CCGR3);
-	__raw_writel(1 << MXC_CCM_CCGR4_CG8_OFFSET, MXC_CCM_CCGR4);
-
-	__raw_writel(1 << MXC_CCM_CCGR5_CG2_OFFSET |
-		     1 << MXC_CCM_CCGR5_CG6_1_OFFSET |
-		     1 << MXC_CCM_CCGR5_CG6_2_OFFSET |
-		     3 << MXC_CCM_CCGR5_CG7_OFFSET |
-		     1 << MXC_CCM_CCGR5_CG8_OFFSET |
-		     3 << MXC_CCM_CCGR5_CG9_OFFSET |
-		     1 << MXC_CCM_CCGR5_CG10_OFFSET |
-		     3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5);
-
-	__raw_writel(1 << MXC_CCM_CCGR6_CG4_OFFSET, MXC_CCM_CCGR6);
-
-	ckil_clk.rate = ckil;
-	osc_clk.rate = osc;
-	ckih_clk.rate = ckih1;
-	ckih2_clk.rate = ckih2;
-
-	clk_tree_init();
-
-	for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
-		clk_register(*clkp);
-
-	/*Setup the LPM bypass bits */
-	reg = __raw_readl(MXC_CCM_CLPCR);
-	reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS
-		| MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
-		| MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS
-		| MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS
-		| MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
-	__raw_writel(reg, MXC_CCM_CLPCR);
-
-	/* Disable the handshake with HSC block as its not
-	  * initialised right now.
-	  */
-	reg = __raw_readl(MXC_CCM_CCDR);
-	reg |= MXC_CCM_CCDR_HSC_HS_MASK;
-	__raw_writel(reg, MXC_CCM_CCDR);
-
-	/* This will propagate to all children and init all the clock rates */
-	propagate_rate(&osc_clk);
-	propagate_rate(&ckih_clk);
-	propagate_rate(&ckih2_clk);
-	propagate_rate(&ckil_clk);
-	propagate_rate(&pll1_sw_clk);
-	propagate_rate(&pll2_sw_clk);
-
-	clk_enable(&cpu_clk);
-	reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL;
-	reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET;
-
-	if (reg)
-		clk_set_parent(&ddr_clk, &ddr_hf_clk);
-	else
-		clk_set_parent(&ddr_clk, &axi_a_clk);
-
-	/* Initialise the parents to be axi_b, parents are set to
-	 * axi_a when the clocks are enabled.
-	 */
-	clk_set_parent(&vpu_clk[0], &axi_b_clk);
-	clk_set_parent(&vpu_clk[1], &axi_b_clk);
-	clk_set_parent(&gpu3d_clk, &axi_a_clk);
-	clk_set_parent(&gpu2d_clk, &axi_a_clk);
-
-	/* move cspi to 24MHz */
-	clk_set_parent(&cspi_main_clk, &lp_apm_clk);
-	clk_set_rate(&cspi_main_clk, 12000000);
-	/*move the spdif0 to spdif_xtal_ckl */
-	clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk);
-	/*set the SPDIF dividers to 1 */
-	reg = __raw_readl(MXC_CCM_CDCDR);
-	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK;
-	__raw_writel(reg, MXC_CCM_CDCDR);
-
-	/* move the spdif1 to 24MHz */
-	clk_set_parent(&spdif1_clk[0], &spdif_xtal_clk);
-	/* set the spdif1 dividers to 1 */
-	reg = __raw_readl(MXC_CCM_CDCDR);
-	reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK;
-	__raw_writel(reg, MXC_CCM_CDCDR);
-
-	/* Move SSI clocks to SSI_LP_APM clock */
-	clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
-
-	clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk);
-	/* set the SSI dividers to divide by 2 */
-	reg = __raw_readl(MXC_CCM_CS1CDR);
-	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK;
-	reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CS1CDR);
-
-	clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk);
-	reg = __raw_readl(MXC_CCM_CS2CDR);
-	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK;
-	reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
-	__raw_writel(reg, MXC_CCM_CS2CDR);
-
-	/* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
-	clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
-	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
-
-	/* move usb_phy_clk to 24MHz */
-	clk_set_parent(&usb_phy_clk, &osc_clk);
-
-	/* set usboh3_clk to pll2 */
-	clk_set_parent(&usboh3_clk[0], &pll2_sw_clk);
-	reg = __raw_readl(MXC_CCM_CSCDR1);
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
-	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
-	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CSCDR1);
-
-	/* Set the current working point. */
-	cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
-	/* Update the cpu working point table based on the PLL1 freq
-	 * at boot time
-	 */
-	if (pll1_main_clk.rate <= cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate)
-		wp_cnt = 1;
-	else if (pll1_main_clk.rate <= cpu_wp_tbl[1].cpu_rate &&
-				pll1_main_clk.rate > cpu_wp_tbl[2].cpu_rate)
-		wp_cnt = cpu_wp_nr - 1;
-	else
-		wp_cnt = cpu_wp_nr;
-
-	cpu_wp_tbl[0].cpu_rate = pll1_main_clk.rate;
-
-	if (wp_cnt == 1) {
-		cpu_wp_tbl[0] = cpu_wp_tbl[cpu_wp_nr - 1];
-		memset(&cpu_wp_tbl[cpu_wp_nr - 1], 0, sizeof(struct cpu_wp));
-		memset(&cpu_wp_tbl[cpu_wp_nr - 2], 0, sizeof(struct cpu_wp));
-	} else if (wp_cnt < cpu_wp_nr) {
-		for (i = 0; i < wp_cnt; i++)
-			cpu_wp_tbl[i] = cpu_wp_tbl[i+1];
-		memset(&cpu_wp_tbl[i], 0, sizeof(struct cpu_wp));
-	}
-
-	if (wp_cnt < cpu_wp_nr) {
-		set_num_cpu_wp(wp_cnt);
-		cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
-	}
-
-
-	for (j = 0; j < cpu_wp_nr; j++) {
-		if ((ddr_clk.parent == &ddr_hf_clk)) {
-			/* Change the CPU podf divider based on the boot up
-			 * pll1 rate.
-			 */
-			cpu_wp_tbl[j].cpu_podf =
-				(pll1_main_clk.rate / cpu_wp_tbl[j].cpu_rate)
-				- 1;
-			if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) >
-					cpu_wp_tbl[j].cpu_rate) {
-				cpu_wp_tbl[j].cpu_podf++;
-				cpu_wp_tbl[j].cpu_rate =
-					 pll1_main_clk.rate/
-					 (1000 * (cpu_wp_tbl[j].cpu_podf + 1));
-				cpu_wp_tbl[j].cpu_rate *= 1000;
-			}
-			if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) <
-						cpu_wp_tbl[j].cpu_rate) {
-				cpu_wp_tbl[j].cpu_rate = pll1_main_clk.rate;
-			}
-		}
-	cpu_wp_tbl[j].pll_rate = pll1_main_clk.rate;
-	}
-	/* Set the current working point. */
-	for (i = 0; i < cpu_wp_nr; i++) {
-		if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) {
-			cpu_curr_wp = i;
-			break;
-		}
-	}
-	if (i > cpu_wp_nr)
-		BUG();
-
-	/*Allow for automatic gating of the EMI internal clock.
-	 * If this is done, emi_intr CCGR bits should be set to 11.
-	 */
-	reg = __raw_readl((IO_ADDRESS(M4IF_BASE_ADDR) + 0x8c));
-	reg &= ~0x1;
-	__raw_writel(reg, (IO_ADDRESS(M4IF_BASE_ADDR) + 0x8c));
-
-	clk_set_parent(&arm_axi_clk, &axi_a_clk);
-	clk_set_parent(&ipu_clk[0], &axi_b_clk);
-
-	if (uart_at_24) {
-		/* Move UART to run from lp_apm */
-		clk_set_parent(&uart_main_clk, &lp_apm_clk);
-
-		/* Set the UART dividers to divide, so the UART_CLK is 24MHz. */
-		reg = __raw_readl(MXC_CCM_CSCDR1);
-		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
-		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
-		reg |= (0 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
-		    (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
-		__raw_writel(reg, MXC_CCM_CSCDR1);
-	} else {
-		/* Move UART to run from PLL1 */
-		clk_set_parent(&uart_main_clk, &pll1_sw_clk);
-
-		/* Set the UART dividers to divide,
-		 * so the UART_CLK is 66.5MHz.
-		 */
-		reg = __raw_readl(MXC_CCM_CSCDR1);
-		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
-		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
-		reg |= (5 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
-		    (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
-		__raw_writel(reg, MXC_CCM_CSCDR1);
-	}
-
-	propagate_rate(&osc_clk);
-	propagate_rate(&pll1_sw_clk);
-	propagate_rate(&pll2_sw_clk);
-
-	clk_set_parent(&emi_slow_clk, &ahb_clk);
-	clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 130000000));
-
-	/* Change the NFC clock rate to be 1:4 ratio with emi clock. */
-	clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk,
-			(clk_get_rate(&emi_slow_clk))/4));
-
-	base = ioremap(GPT1_BASE_ADDR, SZ_4K);
-	mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
-	return 0;
-}
-
-/*!
- * Setup cpu clock based on working point.
- * @param	wp	cpu freq working point
- * @return		0 on success or error code on failure.
- */
-static int cpu_clk_set_wp(int wp)
-{
-	struct cpu_wp *p;
-	u32 reg;
-	u32 stat;
-
-	if (wp == cpu_curr_wp)
-		return 0;
-
-	p = &cpu_wp_tbl[wp];
-
-	/*
-	 * If DDR clock is sourced from PLL1, we cannot drop PLL1 freq.
-	 * Use the ARM_PODF to change the freq of the core, leave the PLL1
-	 * freq unchanged.
-	 */
-	if (ddr_clk.parent == &ddr_hf_clk) {
-		reg = __raw_readl(MXC_CCM_CACRR);
-		reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
-		reg |= cpu_wp_tbl[wp].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
-		__raw_writel(reg, MXC_CCM_CACRR);
-		cpu_curr_wp = wp;
-		cpu_clk.rate = cpu_wp_tbl[wp].cpu_rate;
-	} else {
-		struct timespec nstimeofday;
-		struct timespec curtime;
-
-		/* Change the ARM clock to requested frequency */
-		/* First move the ARM clock to step clock which is running
-		 * at 24MHz.
-		 */
-
-		/* Change the source of pll1_sw_clk to be the step_clk */
-		reg = __raw_readl(MXC_CCM_CCSR);
-		reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-		__raw_writel(reg, MXC_CCM_CCSR);
-
-		/* Stop the PLL */
-		reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL);
-		reg &= ~MXC_PLL_DP_CTL_UPEN;
-		__raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL);
-
-		/* PDF and MFI */
-		reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET;
-		__raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_OP);
-
-		/* MFD */
-		__raw_writel(p->mfd, MXC_DPLL1_BASE + MXC_PLL_DP_MFD);
-
-		/* MFI */
-		__raw_writel(p->mfn, MXC_DPLL1_BASE + MXC_PLL_DP_MFN);
-
-		reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL);
-		reg |= MXC_PLL_DP_CTL_UPEN;
-		/* Set the UPEN bits */
-		__raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL);
-		/* Forcefully restart the PLL */
-		reg |= MXC_PLL_DP_CTL_RST;
-		__raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL);
-
-		/* Wait for the PLL to lock */
-		getnstimeofday(&nstimeofday);
-		do {
-			getnstimeofday(&curtime);
-			if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
-				panic("pll1 relock failed\n");
-			stat = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL) &
-			    MXC_PLL_DP_CTL_LRF;
-		} while (!stat);
-
-		reg = __raw_readl(MXC_CCM_CCSR);
-		/* Move the PLL1 back to the pll1_main_clk */
-		reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-		__raw_writel(reg, MXC_CCM_CCSR);
-
-		cpu_curr_wp = wp;
-
-		pll1_sw_clk.rate = cpu_wp_tbl[wp].cpu_rate;
-		pll1_main_clk.rate = pll1_sw_clk.rate;
-		cpu_clk.rate = pll1_sw_clk.rate;
-	}
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-	cpufreq_trig_needed = 1;
-#endif
-	return 0;
-}
diff --git a/arch/arm/mach-mx51/devices.c b/arch/arm/mach-mx51/devices.c
deleted file mode 100644
index d625c4b0ff61..000000000000
--- a/arch/arm/mach-mx51/devices.c
+++ /dev/null
@@ -1,1352 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/uio_driver.h>
-#include <linux/mxc_scc2_driver.h>
-#include <linux/iram_alloc.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <mach/sdma.h>
-#include "sdma_script_code.h"
-#include "crm_regs.h"
-#include "mx51_pins.h"
-#include "devices.h"
-#include "displays/displays.h"
-#include "linux/fb.h"
-
-/* Flag used to indicate when IRAM has been initialized */
-int iram_ready;
-/* Flag used to indicate if dvfs_core is active. */
-int dvfs_core_is_active;
-
-void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr)
-{
-	/* AP<->BP */
-	sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR;
-	sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
-	sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
-	sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1;
-
-	/*misc */
-	sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
-	sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;
-
-	/* firi */
-	sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
-	sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
-	sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
-	sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;
-
-	/* uart */
-	sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR;
-	sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR;
-
-	/* UART SH */
-	sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR;
-	sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR;
-
-	/* SHP */
-	sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR;
-	sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR;
-	sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR;
-	sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR;
-
-	/* ATA */
-	sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR;
-	sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR;
-
-	/* app */
-	sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR;
-	sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR;
-	sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR;
-	sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR;
-
-	/* MSHC */
-	sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
-	sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;
-
-	/* spdif */
-	sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1;
-	sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR;
-
-	/* IPU */
-	sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR;
-
-	/* DVFS */
-	sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
-
-	/* core */
-	sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code;
-	sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR;
-	sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
-}
-
-#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE)
-
-static struct mxc_w1_config mxc_w1_master_resources = {
-	{
-		.start = OWIRE_BASE_ADDR,
-		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_OWIRE,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device mxc_w1_devices = {
-	.name = "mxc_w1",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
-	.resource = mxc_w1_master_resources,
-};
-#endif
-
-static struct resource mxc_kpp_resources[] = {
-	{
-		.start = KPP_BASE_ADDR,
-		.end = KPP_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_KPP,
-		.end = MXC_INT_KPP,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_keypad_device = {
-	.name = "mxc_keypad",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
-	.resource = mxc_kpp_resources,
-};
-
-static struct resource rtc_resources[] = {
-	{
-	 .start = SRTC_BASE_ADDR,
-	 .end = SRTC_BASE_ADDR + 0x40,
-	 .flags = IORESOURCE_MEM,
-	 },
-	{
-	 .start = MXC_INT_SRTC_NTZ,
-	 .flags = IORESOURCE_IRQ,
-	 },
-};
-
-struct platform_device mxc_rtc_device = {
-	.name = "mxc_rtc",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(rtc_resources),
-	.resource = rtc_resources,
-};
-
-static struct resource imx_nfc_resources[] = {
-	{
-		.flags = IORESOURCE_MEM,
-		.start = NFC_BASE_ADDR_AXI + 0x0000,
-		.end   = NFC_BASE_ADDR_AXI + 0x1200 - 1,
-		.name  = IMX_NFC_BUFFERS_ADDR_RES_NAME,
-	},
-	{
-		.flags = IORESOURCE_MEM,
-		.start = NFC_BASE_ADDR_AXI + 0x1E00,
-		.end   = NFC_BASE_ADDR_AXI + 0x1E44 - 1,
-		.name  = IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME,
-	},
-	{
-		.flags = IORESOURCE_MEM,
-		.start = NFC_BASE_ADDR + 0x00,
-		.end   = NFC_BASE_ADDR + 0x34 - 1,
-		.name  = IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME,
-	},
-	{
-		.flags = IORESOURCE_IRQ,
-		.start = MXC_INT_NFC,
-		.end   = MXC_INT_NFC,
-		.name  = IMX_NFC_INTERRUPT_RES_NAME,
-	},
-};
-
-struct platform_device imx_nfc_device = {
-	.name = IMX_NFC_DRIVER_NAME,
-	.id = 0,
-	.resource      = imx_nfc_resources,
-	.num_resources = ARRAY_SIZE(imx_nfc_resources),
-};
-
-static struct resource wdt_resources[] = {
-	{
-	 .start = WDOG1_BASE_ADDR,
-	 .end = WDOG1_BASE_ADDR + 0x30,
-	 .flags = IORESOURCE_MEM,
-	 },
-};
-
-struct platform_device mxc_wdt_device = {
-	.name = "mxc_wdt",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(wdt_resources),
-	.resource = wdt_resources,
-};
-
-static struct resource pwm1_resources[] = {
-	{
-		.start = PWM1_BASE_ADDR,
-		.end = PWM1_BASE_ADDR + 0x14,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_PWM1,
-		.end = MXC_INT_PWM1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_pwm1_device = {
-	.name = "mxc_pwm",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(pwm1_resources),
-	.resource = pwm1_resources,
-};
-
-static struct resource pwm2_resources[] = {
-	{
-		.start = PWM2_BASE_ADDR,
-		.end = PWM2_BASE_ADDR + 0x14,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_PWM2,
-		.end = MXC_INT_PWM2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_pwm2_device = {
-	.name = "mxc_pwm",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(pwm2_resources),
-	.resource = pwm2_resources,
-};
-
-struct platform_device mxc_pwm_backlight_device = {
-	.name = "pwm-backlight",
-	.id = -1,
-};
-
-static struct resource ipu_resources[] = {
-	{
-	 .start = IPU_CTRL_BASE_ADDR,
-	 .end = IPU_CTRL_BASE_ADDR + SZ_512M,
-	 .flags = IORESOURCE_MEM,
-	 },
-	{
-	 .start = MXC_INT_IPU_SYN,
-	 .flags = IORESOURCE_IRQ,
-	 },
-	{
-	 .start = MXC_INT_IPU_ERR,
-	 .flags = IORESOURCE_IRQ,
-	 },
-};
-
-struct platform_device mxc_ipu_device = {
-	.name = "mxc_ipu",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(ipu_resources),
-	.resource = ipu_resources,
-};
-
-static struct resource vpu_resources[] = {
-	{
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = (resource_size_t)IO_ADDRESS(SRC_BASE_ADDR),
-		.end = (resource_size_t)IO_ADDRESS(SRC_BASE_ADDR),
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start	= MXC_INT_VPU_IDLE,
-		.end	= MXC_INT_VPU_IDLE,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxcvpu_device = {
-	.name = "mxc_vpu",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(vpu_resources),
-	.resource = vpu_resources,
-};
-
-static struct resource mxcspi1_resources[] = {
-	{
-		.start = CSPI1_BASE_ADDR,
-		.end = CSPI1_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_CSPI1,
-		.end = MXC_INT_CSPI1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxcspi1_device = {
-	.name = "mxc_spi",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxcspi1_resources),
-	.resource = mxcspi1_resources,
-};
-
-
-static struct resource mxcspi2_resources[] = {
-	{
-		.start = CSPI2_BASE_ADDR,
-		.end = CSPI2_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_CSPI2,
-		.end = MXC_INT_CSPI2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxcspi2_device = {
-	.name = "mxc_spi",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(mxcspi2_resources),
-	.resource = mxcspi2_resources,
-};
-
-static struct resource mxcspi3_resources[] = {
-	{
-		.start = CSPI3_BASE_ADDR,
-		.end = CSPI3_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_CSPI,
-		.end = MXC_INT_CSPI,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxcspi3_device = {
-	.name = "mxc_spi",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxcspi3_resources),
-	.resource = mxcspi3_resources,
-};
-
-static struct resource mxci2c1_resources[] = {
-	{
-		.start = I2C1_BASE_ADDR,
-		.end = I2C1_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_I2C1,
-		.end = MXC_INT_I2C1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource mxci2c2_resources[] = {
-	{
-		.start = I2C2_BASE_ADDR,
-		.end = I2C2_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_I2C2,
-		.end = MXC_INT_I2C2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxci2c_devices[] = {
-	{
-		.name = "mxc_i2c",
-		.id = 0,
-		.num_resources = ARRAY_SIZE(mxci2c1_resources),
-		.resource = mxci2c1_resources,
-	},
-	{
-		.name = "mxc_i2c",
-		.id = 1,
-		.num_resources = ARRAY_SIZE(mxci2c2_resources),
-		.resource = mxci2c2_resources,
-	},
-};
-
-static struct resource mxci2c_hs_resources[] = {
-	{
-		.start = HSI2C_DMA_BASE_ADDR,
-		.end = HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_HS_I2C,
-		.end = MXC_INT_HS_I2C,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxci2c_hs_device = {
-	.name = "mxc_i2c_hs",
-	.id = 3,
-	.num_resources = ARRAY_SIZE(mxci2c_hs_resources),
-	.resource = mxci2c_hs_resources
-};
-
-static struct resource ssi1_resources[] = {
-	{
-		.start = SSI1_BASE_ADDR,
-		.end = SSI1_BASE_ADDR + 0x5C,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_SSI1,
-		.end = MXC_INT_SSI1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_ssi1_device = {
-	.name = "mxc_ssi",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(ssi1_resources),
-	.resource = ssi1_resources,
-};
-
-static struct resource ssi2_resources[] = {
-	{
-		.start = SSI2_BASE_ADDR,
-		.end = SSI2_BASE_ADDR + 0x5C,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_SSI2,
-		.end = MXC_INT_SSI2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_ssi2_device = {
-	.name = "mxc_ssi",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(ssi2_resources),
-	.resource = ssi2_resources,
-};
-
-static struct resource tve_resources[] = {
-	{
-		.start = TVE_BASE_ADDR,
-		.end = TVE_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_TVE,
-		.end = MXC_INT_TVE,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_tve_device = {
-	.name = "tve",
-	.num_resources = ARRAY_SIZE(tve_resources),
-	.resource = tve_resources,
-};
-
-static struct resource dvfs_core_resources[] = {
-	{
-		.start = (resource_size_t)MXC_DVFS_CORE_BASE,
-		.end = (resource_size_t)MXC_DVFS_CORE_BASE + 4 * SZ_16 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_GPC1,
-		.end = MXC_INT_GPC1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_dvfs_core_device = {
-	.name = "mxc_dvfs_core",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(dvfs_core_resources),
-	.resource = dvfs_core_resources,
-};
-
-static struct resource dvfs_per_resources[] = {
-	{
-		.start = DVFSPER_BASE_ADDR,
-		.end = DVFSPER_BASE_ADDR + 2 * SZ_16 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_GPC1,
-		.end = MXC_INT_GPC1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_dvfs_per_device = {
-	 .name = "mxc_dvfsper",
-	 .id = 0,
-	 .num_resources = ARRAY_SIZE(dvfs_per_resources),
-	 .resource = dvfs_per_resources,
-};
-
-struct mxc_gpio_port mxc_gpio_ports[] = {
-	{
-		.chip.label = "gpio-0",
-		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
-		.irq = MXC_INT_GPIO1_LOW,
-		.irq_high = MXC_INT_GPIO1_HIGH,
-		.virtual_irq_start = MXC_GPIO_IRQ_START
-	},
-	{
-		.chip.label = "gpio-1",
-		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
-		.irq = MXC_INT_GPIO2_LOW,
-		.irq_high = MXC_INT_GPIO2_HIGH,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
-	},
-	{
-		.chip.label = "gpio-2",
-		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
-		.irq = MXC_INT_GPIO3_LOW,
-		.irq_high = MXC_INT_GPIO3_HIGH,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
-	},
-	{
-		.chip.label = "gpio-3",
-		.base = IO_ADDRESS(GPIO4_BASE_ADDR),
-		.irq = MXC_INT_GPIO4_LOW,
-		.irq_high = MXC_INT_GPIO4_HIGH,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
-	},
-};
-
-int __init mxc_register_gpios(void)
-{
-	return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
-}
-
-static struct resource spdif_resources[] = {
-	{
-		.start = SPDIF_BASE_ADDR,
-		.end = SPDIF_BASE_ADDR + 0x50,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_SPDIF,
-		.end = MXC_INT_SPDIF,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_alsa_spdif_device = {
-	.name = "mxc_alsa_spdif",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(spdif_resources),
-	.resource = spdif_resources,
-};
-
-
-struct platform_device mx51_lpmode_device = {
-	.name = "mx51_lpmode",
-	.id = 0,
-};
-
-
-struct platform_device busfreq_device = {
-	.name = "busfreq",
-	.id = 0,
-};
-
-static struct resource mxc_m4if_resources[] = {
-	{
-	 .start = M4IF_BASE_ADDR,
-	 .end = M4IF_BASE_ADDR + SZ_4K - 1,
-	 .flags = IORESOURCE_MEM,
-	 },
-};
-
-struct platform_device sdram_autogating_device = {
-	.name = "sdram_autogating",
-	.id = 0,
-	.resource = mxc_m4if_resources,
-	.num_resources = ARRAY_SIZE(mxc_m4if_resources),
-};
-
-static struct resource mxc_iim_resources[] = {
-	{
-	 .start = IIM_BASE_ADDR,
-	 .end = IIM_BASE_ADDR + SZ_4K - 1,
-	 .flags = IORESOURCE_MEM,
-	 },
-};
-
-struct platform_device mxc_iim_device = {
-	.name = "mxc_iim",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_iim_resources),
-	.resource = mxc_iim_resources
-};
-
-static struct resource mxc_sim_resources[] = {
-	{
-		.start = SIM_BASE_ADDR,
-		.end = SIM_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_SIM_IPB,
-		.end = MXC_INT_SIM_IPB,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = MXC_INT_SIM_DAT,
-		.end = MXC_INT_SIM_DAT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_sim_device = {
-	.name = "mxc_sim",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_sim_resources),
-	.resource = mxc_sim_resources,
-};
-
-#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
-
-/**
- * Resource definition for the SDHC1
- */
-static struct resource mxcsdhc1_resources[] = {
-	{
-		.start = MMC_SDHC1_BASE_ADDR,
-		.end   = MMC_SDHC1_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_MMC_SDHC1,
-		.end   = MXC_INT_MMC_SDHC1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0),
-		.end   = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0),
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-/**
- * Resource definition for the SDHC3
- */
-static struct resource mxcsdhc3_resources[] = {
-	{
-		.start = MMC_SDHC3_BASE_ADDR,
-		.end   = MMC_SDHC3_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_MMC_SDHC3,
-		.end   = MXC_INT_MMC_SDHC3,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND),
-		.end   = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND),
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-/*! Device Definition for MXC SDHC1 */
-struct platform_device mxcsdhc1_device = {
-	.name = "mxsdhci",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
-	.resource = mxcsdhc1_resources,
-};
-
-/*! Device Definition for MXC SDHC3 */
-struct platform_device mxcsdhc3_device = {
-	.name = "mxsdhci",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxcsdhc3_resources),
-	.resource = mxcsdhc3_resources,
-};
-
-#endif
-
-static struct resource pata_fsl_resources[] = {
-	{
-		.start = ATA_BASE_ADDR,
-		.end = ATA_BASE_ADDR + 0x000000C8,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_ATA,
-		.end = MXC_INT_ATA,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device pata_fsl_device = {
-	.name = "pata_fsl",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(pata_fsl_resources),
-	.resource = pata_fsl_resources,
-	.dev = {
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-static u64 usb_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource usbotg_resources[] = {
-	{
-		.start = OTG_BASE_ADDR,
-		.end = OTG_BASE_ADDR + 0x1ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_USB_OTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource usbotg_xcvr_resources[] = {
-	{
-		.start = OTG_BASE_ADDR,
-		.end = OTG_BASE_ADDR + 0x1ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_USB_OTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_usbdr_udc_device = {
-	.name = "fsl-usb2-udc",
-	.id   = -1,
-	.dev  = {
-		.dma_mask = &usb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-	.resource      = usbotg_resources,
-	.num_resources = ARRAY_SIZE(usbotg_resources),
-};
-
-struct platform_device mxc_usbdr_otg_device = {
-	.name = "fsl-usb2-otg",
-	.id = -1,
-	.dev = {
-		.dma_mask = &usb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-	.resource      = usbotg_xcvr_resources,
-	.num_resources = ARRAY_SIZE(usbotg_xcvr_resources),
-};
-
-struct platform_device mxc_usbdr_host_device = {
-	.name = "fsl-ehci",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(usbotg_resources),
-	.resource = usbotg_resources,
-	.dev = {
-		.dma_mask = &usb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-static struct resource usbh1_resources[] = {
-	{
-		.start = OTG_BASE_ADDR + 0x200,
-		.end = OTG_BASE_ADDR + 0x200 + 0x1ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_USB_H1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_usbh1_device = {
-	.name = "fsl-ehci",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(usbh1_resources),
-	.resource = usbh1_resources,
-	.dev = {
-		.dma_mask = &usb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-static struct resource usbh2_resources[] = {
-	{
-		.start = OTG_BASE_ADDR + 0x400,
-		.end = OTG_BASE_ADDR + 0x400 + 0x1ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_USB_H2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_usbh2_device = {
-	.name = "fsl-ehci",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(usbh2_resources),
-	.resource = usbh2_resources,
-	.dev = {
-		.dma_mask = &usb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-static struct resource mxc_gpu_resources[] = {
-	{
-		.start = MXC_INT_GPU2_IRQ,
-		.end = MXC_INT_GPU2_IRQ,
-		.name = "gpu_2d_irq",
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = MXC_INT_GPU,
-		.end = MXC_INT_GPU,
-		.name = "gpu_3d_irq",
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = GPU2D_BASE_ADDR,
-		.end = GPU2D_BASE_ADDR + SZ_4K - 1,
-		.name = "gpu_2d_registers",
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = GPU_BASE_ADDR,
-		.end = GPU_BASE_ADDR + SZ_128K - 1,
-		.name = "gpu_3d_registers",
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = GPU_GMEM_BASE_ADDR,
-		.end = GPU_GMEM_BASE_ADDR + SZ_128K - 1,
-		.name = "gpu_graphics_mem",
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-struct platform_device gpu_device = {
-	.name = "mxc_gpu",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_gpu_resources),
-	.resource = mxc_gpu_resources,
-};
-
-
-#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE)
-static struct clk *gpu_clk;
-
-static struct resource mxc_gpu2d_resources[] = {
-	{
-	 .start = GPU2D_BASE_ADDR,
-	 .end = GPU2D_BASE_ADDR + SZ_4K - 1,
-	 .flags = IORESOURCE_MEM,
-	 },
-	{
-	 .flags = IORESOURCE_MEM,
-	 },
-	{
-	 .flags = IORESOURCE_MEM,
-	 },
-};
-
-int gpu2d_open(struct uio_info *info, struct inode *inode)
-{
-	gpu_clk = clk_get(NULL, "gpu2d_clk");
-	if (IS_ERR(gpu_clk))
-		return PTR_ERR(gpu_clk);
-
-	return clk_enable(gpu_clk);
-}
-
-int gpu2d_release(struct uio_info *info, struct inode *inode)
-{
-	if (IS_ERR(gpu_clk))
-		return PTR_ERR(gpu_clk);
-
-	clk_disable(gpu_clk);
-	clk_put(gpu_clk);
-	return 0;
-}
-
-static int gpu2d_mmap(struct uio_info *info, struct vm_area_struct *vma)
-{
-	int mi = vma->vm_pgoff;
-	if (mi < 0)
-		return -EINVAL;
-
-	vma->vm_flags |= VM_IO | VM_RESERVED;
-	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-
-	return remap_pfn_range(vma,
-			       vma->vm_start,
-			       info->mem[mi].addr >> PAGE_SHIFT,
-			       vma->vm_end - vma->vm_start,
-			       vma->vm_page_prot);
-}
-
-struct platform_device mxc_gpu2d_device = {
-	.name = "uio_pdrv_genirq",
-	.dev = {
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		},
-	.num_resources = ARRAY_SIZE(mxc_gpu2d_resources),
-	.resource = mxc_gpu2d_resources,
-};
-
-static inline void mxc_init_gpu2d(void)
-{
-	dma_alloc_coherent(&mxc_gpu2d_device.dev, SZ_8K, &mxc_gpu2d_resources[1].start, GFP_DMA);
-	mxc_gpu2d_resources[1].end = mxc_gpu2d_resources[1].start + SZ_8K - 1;
-
-	dma_alloc_coherent(&mxc_gpu2d_device.dev, 88 * SZ_1K, &mxc_gpu2d_resources[2].start, GFP_DMA);
-	mxc_gpu2d_resources[2].end = mxc_gpu2d_resources[2].start + (88 * SZ_1K) - 1;
-}
-#endif
-
-/* MTD NAND flash */
-#if defined(CONFIG_MTD_NAND_MXC) \
-	|| defined(CONFIG_MTD_NAND_MXC_MODULE) \
-	|| defined(CONFIG_MTD_NAND_MXC_V2) \
-	|| defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \
-	|| defined(CONFIG_MTD_NAND_MXC_V3) \
-	|| defined(CONFIG_MTD_NAND_MXC_V3_MODULE)
-
-struct platform_device mxc_nandv2_mtd_device = {
-	.name = "mxc_nandv2_flash",
-	.id = 0,
-};
-#endif
-
-#if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE)
-struct platform_device mxc_wm8753_device = {
-	.name = "ccwmx51js",
-};
-#endif
-
-#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
-static struct resource smsc911x_device_resources[] = {
-	{
-		.name	= "smsc911x-memory",
-		.start	= CS5_BASE_ADDR,
-		.end	= CS5_BASE_ADDR + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
-		.end	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-        .name             = "smsc911x",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(smsc911x_device_resources),
-        .resource         = smsc911x_device_resources,
-};
-
-/* WEIM registers */
-#define CSGCR1	0x00
-#define CSGCR2	0x04
-#define CSRCR1	0x08
-#define CSRCR2	0x0C
-#define CSWCR1	0x10
-
-static void ccwmx51_init_ext_eth_mac(void)
-{
-	__iomem u32 *weim_vbaddr;
-
-	weim_vbaddr = ioremap(WEIM_BASE_ADDR, SZ_4K);
-	if (weim_vbaddr == 0) {
-		printk(KERN_ERR "Unable to ioremap 0x%08x in %s\n", WEIM_BASE_ADDR, __func__);
-		return;
-	}
-
-	/** Configure the CS timming, bus width, etc.
-	 * 16 bit on DATA[31..16], not multiplexed, async
-	 * RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0, APR=0
-	 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0
-	 */
-	writel(0x00420081, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR1);
-	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR2);
-	writel(0x32260000, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR1);
-	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR2);
-	writel(0x72080f00, (unsigned int)(weim_vbaddr) + 0x78 + CSWCR1);
-
-	iounmap(weim_vbaddr);
-
-	/* Configure interrupt line as GPIO input, the iomux should be already setup */
-	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9), "LAN2-irq");
-	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9));
-}
-#endif
-
-#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
-static struct resource mxc_fec_resources[] = {
-	{
-		.start	= FEC_BASE_ADDR,
-		.end	= FEC_BASE_ADDR + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM
-	}, {
-		.start	= MXC_INT_FEC,
-		.end	= MXC_INT_FEC,
-		.flags	= IORESOURCE_IRQ
-	},
-};
-
-struct platform_device mxc_fec_device = {
-	.name = "fec",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_fec_resources),
-	.resource = mxc_fec_resources,
-};
-#endif
-
-#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
-	defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
-
-struct platform_device mxc_fb_devices[] = {
-	{
-		.name = "mxc_sdc_fb",
-		.id = 0,
-		.dev = {
-			.coherent_dma_mask = DMA_BIT_MASK(32),
-		},
-	 }, {
-		.name = "mxc_sdc_fb",
-		.id = 1,
-		.dev = {
-			.coherent_dma_mask = DMA_BIT_MASK(32),
-		},
-	}, {
-		.name = "mxc_sdc_fb",
-		.id = 2,
-		.dev = {
-			.coherent_dma_mask = DMA_BIT_MASK(32),
-		},
-	},
-};
-
-struct platform_device lcd_pdev = {
-	.name = "ccwmx51_display",
-	.dev = {
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct ccwmx51_lcd_pdata * ccwmx51_get_display(char *name)
-{
-#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) || defined(CONFIG_CCWMX51_CUSTOM)
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(lcd_display_list); i++)
-		if (!strncmp(lcd_display_list[i].fb_pdata.mode->name,
-			     name, strlen(lcd_display_list[i].fb_pdata.mode->name)))
-			return &lcd_display_list[i];
-#endif
-	return NULL;
-}
-
-static int __init ccwmx51_init_fb(void)
-{
-	char *options = NULL, *p;
-
-	if (fb_get_options("displayfb", &options))
-		pr_warning("no display information available in command line\n");
-
-	if (!options)
-		return -ENODEV;
-
-	if (!strncasecmp(options, "VGA", 3)) {
-		pr_info("VGA interface is primary\n");
-
-		/* Get the desired configuration provided by the bootloader */
-		if (options[3] != '@') {
-			pr_info("Video resolution for VGA interface not provided, using default\n");
-			/* TODO set default video here */
-		} else {
-			options = &options[4];
-			if (((p = strsep (&options, "@")) != NULL) && *p) {
-				if (!strcmp(p, "640x480x16")) {
-					strcpy(mx51_fb_data[0].mode_str, "640x480M-16@60");
-				} else if (!strcmp(p, "800x600x16")) {
-					strcpy(mx51_fb_data[0].mode_str, "800x600M-16@60");
-				} else if (!strcmp(p, "1024x768x16")) {
-					strcpy(mx51_fb_data[0].mode_str, "1024x768M-16@60");
-				} else if (!strcmp(p, "1280x1024x16")) {
-					strcpy(mx51_fb_data[0].mode_str, "1280x1024M-16@60");
-				} else
-					pr_warning("Unsuported video resolution: %s, using default\n", p);
-			}
-		}
-	} else {
-		if ((plcd_platform_data = ccwmx51_get_display(options)) != NULL) {
-			memcpy(&mx51_fb_data[0], &plcd_platform_data->fb_pdata, sizeof(struct mxc_fb_platform_data));
-			plcd_platform_data->vif = 0;	/* Select video interface 0 */
-		}
-	}
-	return 0;
-}
-device_initcall(ccwmx51_init_fb);
-
-#endif
-
-struct platform_device mxc_dma_device = {
-     .name = "mxc_dma",
-     .id = 0,
-};
-
-void __init mx51_init_irq(void)
-{
-	unsigned long tzic_addr;
-
-	if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
-		tzic_addr = TZIC_BASE_ADDR_T01;
-	else
-		tzic_addr = TZIC_BASE_ADDR;
-
-	mxc_tzic_init_irq(tzic_addr);
-}
-
-#define SCM_RD_DELAY	1000000 /* in nanoseconds */
-#define SEC_TO_NANOSEC  1000000000 /*Second to nanoseconds */
-static __init void mxc_init_scc_iram(void)
-{
-	uint32_t reg_value;
-	uint32_t reg_mask = 0;
-	uint8_t *UMID_base;
-	uint32_t *MAP_base;
-	uint8_t i;
-	uint32_t partition_no;
-	uint32_t scc_partno;
-	void *scm_ram_base;
-	void *scc_base;
-	uint8_t iram_partitions = 16;
-	struct timespec stime;
-	struct timespec curtime;
-	long scm_rd_timeout = 0;
-	long cur_ns = 0;
-	long start_ns = 0;
-
-	if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
-		iram_partitions = 12;
-
-	scc_base = ioremap((uint32_t) SCC_BASE_ADDR, 0x140);
-	if (scc_base == NULL) {
-		printk(KERN_ERR "FAILED TO MAP IRAM REGS\n");
-		return;
-	}
-	scm_ram_base = ioremap((uint32_t) IRAM_BASE_ADDR, IRAM_SIZE);
-	if (scm_ram_base == NULL) {
-		printk(KERN_ERR "FAILED TO MAP IRAM\n");
-		return;
-	}
-
-	/* Wait for any running SCC operations to finish or fail */
-	getnstimeofday(&stime);
-	do {
-		reg_value = __raw_readl(scc_base + SCM_STATUS_REG);
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec > stime.tv_nsec)
-			scm_rd_timeout = curtime.tv_nsec - stime.tv_nsec;
-		else{
-			/*Converted second to nanosecond and add to
-			nsec when current nanosec is less than
-			start time nanosec.*/
-			cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) +
-			curtime.tv_nsec;
-			start_ns = (stime.tv_sec * SEC_TO_NANOSEC) +
-				stime.tv_nsec;
-			scm_rd_timeout = cur_ns - start_ns;
-		}
-	} while (((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY)
-	&& ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_FAIL));
-
-	/* Check for failures */
-	if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) {
-		/* Special message for bad secret key fuses */
-		if (reg_value & SCM_STATUS_KST_BAD_KEY)
-			printk(KERN_ERR "INVALID SCC KEY FUSE PATTERN\n");
-		else
-		    printk(KERN_ERR "SECURE RAM FAILURE\n");
-
-		iounmap(scm_ram_base);
-		iounmap(scc_base);
-		return;
-	}
-
-	scm_rd_timeout = 0;
-	/* Release final two partitions for SCC2 driver */
-	scc_partno = iram_partitions - (SCC_IRAM_SIZE / SZ_8K);
-	for (partition_no = scc_partno; partition_no < iram_partitions;
-	     partition_no++) {
-		reg_value = (((partition_no << SCM_ZCMD_PART_SHIFT) &
-			SCM_ZCMD_PART_MASK) | ((0x03 << SCM_ZCMD_CCMD_SHIFT) &
-			SCM_ZCMD_CCMD_MASK));
-		__raw_writel(reg_value, scc_base + SCM_ZCMD_REG);
-		udelay(1);
-		/* Wait for zeroization to complete */
-		getnstimeofday(&stime);
-		do {
-			reg_value = __raw_readl(scc_base + SCM_STATUS_REG);
-			getnstimeofday(&curtime);
-			if (curtime.tv_nsec > stime.tv_nsec)
-				scm_rd_timeout = curtime.tv_nsec -
-				stime.tv_nsec;
-			else {
-				/*Converted second to nanosecond and add to
-				nsec when current nanosec is less than
-				start time nanosec.*/
-				cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) +
-				curtime.tv_nsec;
-				start_ns = (stime.tv_sec * SEC_TO_NANOSEC) +
-					stime.tv_nsec;
-				scm_rd_timeout = cur_ns - start_ns;
-			}
-		} while (((reg_value & SCM_STATUS_SRS_MASK) !=
-		SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) !=
-		SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY));
-
-		if (scm_rd_timeout > SCM_RD_DELAY)
-			printk(KERN_ERR "SCM Status Register Read timeout"
-			"for Partition No:%d", partition_no);
-
-		if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY)
-			break;
-	}
-
-	/*Check all expected partitions released */
-	reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG);
-	if ((reg_value & reg_mask) != 0) {
-		printk(KERN_ERR "FAILED TO RELEASE IRAM PARTITION\n");
-		iounmap(scm_ram_base);
-		iounmap(scc_base);
-		return;
-	}
-	reg_mask = 0;
-	scm_rd_timeout = 0;
-	/* Allocate remaining partitions for general use */
-	for (partition_no = 0; partition_no < scc_partno; partition_no++) {
-		/* Supervisor mode claims a partition for it's own use
-		by writing zero to SMID register.*/
-		__raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no));
-
-		/* Wait for any zeroization to complete */
-		getnstimeofday(&stime);
-		do {
-			reg_value = __raw_readl(scc_base + SCM_STATUS_REG);
-			getnstimeofday(&curtime);
-			if (curtime.tv_nsec > stime.tv_nsec)
-				scm_rd_timeout = curtime.tv_nsec -
-				stime.tv_nsec;
-			else{
-				/*Converted second to nanosecond and add to
-				nsec when current nanosec is less than
-				start time nanosec.*/
-				cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) +
-				curtime.tv_nsec;
-				start_ns = (stime.tv_sec * SEC_TO_NANOSEC) +
-					stime.tv_nsec;
-				scm_rd_timeout = cur_ns - start_ns;
-			}
-		} while (((reg_value & SCM_STATUS_SRS_MASK) !=
-		SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) !=
-		SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY));
-
-		if (scm_rd_timeout > SCM_RD_DELAY)
-			printk(KERN_ERR "SCM Status Register Read timeout"
-			"for Partition No:%d", partition_no);
-
-		if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY)
-			break;
-		/* Set UMID=0 and permissions for universal data
-		read/write access */
-		MAP_base = scm_ram_base + (partition_no * 0x2000);
-		UMID_base = (uint8_t *) MAP_base + 0x10;
-		for (i = 0; i < 16; i++)
-			UMID_base[i] = 0;
-
-		MAP_base[0] = (SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE |
-			SCM_PERM_HD_READ | SCM_PERM_HD_WRITE |
-			SCM_PERM_HD_EXECUTE | SCM_PERM_TH_READ |
-			SCM_PERM_TH_WRITE);
-		reg_mask |= (3 << (2 * (partition_no)));
-	}
-
-	/* Check all expected partitions allocated */
-	reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG);
-	if ((reg_value & reg_mask) != reg_mask) {
-		printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n");
-		iounmap(scm_ram_base);
-		iounmap(scc_base);
-		return;
-	}
-
-	iounmap(scm_ram_base);
-	iounmap(scc_base);
-	printk(KERN_INFO "IRAM READY\n");
-	iram_ready = 1;
-}
-
-int __init mxc_init_devices(void)
-{
-	unsigned long addr;
-
-	iram_alloc(VPU_IRAM_SIZE, &addr);
-	vpu_resources[0].start = addr;
-	vpu_resources[0].end = addr + VPU_IRAM_SIZE - 1;
-
-	mxc_init_scc_iram();
-#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE)
-	mxc_init_gpu2d();
-#endif
-#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
-	ccwmx51_init_ext_eth_mac();
-#endif
-	return 0;
-}
-postcore_initcall(mxc_init_devices);
-
diff --git a/arch/arm/mach-mx51/devices.h b/arch/arm/mach-mx51/devices.h
deleted file mode 100644
index b9b1138580a7..000000000000
--- a/arch/arm/mach-mx51/devices.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-extern struct platform_device mxc_w1_master_device;
-extern struct platform_device mxc_keypad_device;
-extern struct platform_device mxc_rtc_device;
-extern struct platform_device mxc_nandv2_mtd_device;
-extern struct platform_device imx_nfc_device;
-extern struct platform_device mxc_wdt_device;
-extern struct platform_device mxc_pwm1_device;
-extern struct platform_device mxc_pwm2_device;
-extern struct platform_device mxc_pwm_backlight_device;
-extern struct platform_device mxc_ipu_device;
-extern struct platform_device mxc_fb_devices[];
-extern struct platform_device mxcvpu_device;
-extern struct platform_device mxcspi1_device;
-extern struct platform_device mxcspi2_device;
-extern struct platform_device mxcspi3_device;
-extern struct platform_device mxci2c_devices[];
-extern struct platform_device mxci2c_hs_device;
-extern struct platform_device mxc_tve_device;
-extern struct platform_device mxc_dvfs_core_device;
-extern struct platform_device mxc_dvfs_per_device;
-extern struct platform_device mxc_ssi1_device;
-extern struct platform_device mxc_ssi2_device;
-extern struct platform_device mxc_alsa_spdif_device;
-extern struct platform_device mx51_lpmode_device;
-extern struct platform_device busfreq_device;
-extern struct platform_device sdram_autogating_device;
-extern struct platform_device mxc_iim_device;
-extern struct platform_device mxc_sim_device;
-extern struct platform_device mxcsdhc1_device;
-extern struct platform_device mxcsdhc3_device;
-extern struct platform_device lcd_pdev;
-extern struct platform_device pata_fsl_device;
-extern struct platform_device mxc_gpu2d_device;
-extern struct platform_device mxc_wm8753_device;
-extern struct platform_device gpu_device;
-extern struct platform_device mxc_fec_device;
-extern struct platform_device mxc_usbdr_udc_device;
-extern struct platform_device mxc_usbdr_otg_device;
-extern struct platform_device mxc_usbdr_host_device;
-extern struct platform_device mxc_usbh1_device;
-extern struct platform_device mxc_usbh2_device;
-extern struct platform_device mxc_dma_device;
-extern struct mxc_fb_platform_data mx51_fb_data[];
-extern struct ccwmx51_lcd_pdata * plcd_platform_data;
diff --git a/arch/arm/mach-mx51/dummy_gpio.c b/arch/arm/mach-mx51/dummy_gpio.c
deleted file mode 100644
index 8eb771d29a06..000000000000
--- a/arch/arm/mach-mx51/dummy_gpio.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-
-void gpio_gps_active(void) {}
-EXPORT_SYMBOL(gpio_gps_active);
-
-void gpio_gps_inactive(void) {}
-EXPORT_SYMBOL(gpio_gps_inactive);
-
-void config_uartdma_event(int port) {}
-EXPORT_SYMBOL(config_uartdma_event);
-
-void gpio_spi_active(int cspi_mod) {}
-EXPORT_SYMBOL(gpio_spi_active);
-
-void gpio_spi_inactive(int cspi_mod) {}
-EXPORT_SYMBOL(gpio_spi_inactive);
-
-void gpio_owire_active(void) {}
-EXPORT_SYMBOL(gpio_owire_active);
-
-void gpio_owire_inactive(void) {}
-EXPORT_SYMBOL(gpio_owire_inactive);
-
-void gpio_i2c_active(int i2c_num) {}
-EXPORT_SYMBOL(gpio_i2c_active);
-
-void gpio_i2c_inactive(int i2c_num) {}
-EXPORT_SYMBOL(gpio_i2c_inactive);
-
-void gpio_i2c_hs_active(void) {}
-EXPORT_SYMBOL(gpio_i2c_hs_active);
-
-void gpio_i2c_hs_inactive(void) {}
-EXPORT_SYMBOL(gpio_i2c_hs_inactive);
-
-void gpio_pmic_active(void) {}
-EXPORT_SYMBOL(gpio_pmic_active);
-
-void gpio_activate_audio_ports(void) {}
-EXPORT_SYMBOL(gpio_activate_audio_ports);
-
-void gpio_sdhc_active(int module) {}
-EXPORT_SYMBOL(gpio_sdhc_active);
-
-void gpio_sdhc_inactive(int module) {}
-EXPORT_SYMBOL(gpio_sdhc_inactive);
-
-void gpio_sensor_select(int sensor) {}
-
-void gpio_sensor_active(unsigned int csi) {}
-EXPORT_SYMBOL(gpio_sensor_active);
-
-void gpio_sensor_inactive(unsigned int csi) {}
-EXPORT_SYMBOL(gpio_sensor_inactive);
-
-void gpio_ata_active(void) {}
-EXPORT_SYMBOL(gpio_ata_active);
-
-void gpio_ata_inactive(void) {}
-EXPORT_SYMBOL(gpio_ata_inactive);
-
-void gpio_nand_active(void) {}
-EXPORT_SYMBOL(gpio_nand_active);
-
-void gpio_nand_inactive(void) {}
-EXPORT_SYMBOL(gpio_nand_inactive);
-
-void gpio_keypad_active(void) {}
-EXPORT_SYMBOL(gpio_keypad_active);
-
-void gpio_keypad_inactive(void) {}
-EXPORT_SYMBOL(gpio_keypad_inactive);
-
-int gpio_usbotg_hs_active(void)
-{
-	return 0;
-}
-EXPORT_SYMBOL(gpio_usbotg_hs_active);
-
-void gpio_usbotg_hs_inactive(void) {}
-EXPORT_SYMBOL(gpio_usbotg_hs_inactive);
-
-void gpio_fec_active(void) {}
-EXPORT_SYMBOL(gpio_fec_active);
-
-void gpio_fec_inactive(void) {}
-EXPORT_SYMBOL(gpio_fec_inactive);
-
-void gpio_spdif_active(void) {}
-EXPORT_SYMBOL(gpio_spdif_active);
-
-void gpio_spdif_inactive(void) {}
-EXPORT_SYMBOL(gpio_spdif_inactive);
diff --git a/arch/arm/mach-mx51/mx51_pins.h b/arch/arm/mach-mx51/mx51_pins.h
deleted file mode 100644
index 0072da975894..000000000000
--- a/arch/arm/mach-mx51/mx51_pins.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
-
-/*!
- * @file arch-mxc/mx51_pins.h
- *
- * @brief MX51 I/O Pin List
- *
- * @ingroup GPIO_MX51
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I  | GPIO_I | PAD_I  | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I			0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I			10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I			21
-
-#define NON_GPIO_PORT		0x7
-#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I		PIN_TO_MUX_MASK
-#define MUX_I_START		0x001C
-#define PAD_I_START		0x3F0
-#define INPUT_CTL_START		0x8C4
-#define INPUT_CTL_START_TO1	0x928
-#define MUX_I_END		(PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-    _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-    _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
-	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 0, 0x12C, 0x514),
-	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x1C4, 0x5AC),
-	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x1C8, 0x5B0),
-	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-	MX51_PIN_CSI2_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1D4, 0x5C4),
-	MX51_PIN_CSI2_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1D8, 0x5C8),
-	MX51_PIN_CSI2_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1DC, 0x5CC),
-	MX51_PIN_CSI2_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1E0, 0x5D0),
-	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_GPIO_PIN(0, 10, 7, 0x380, 0x788),
-	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-};
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX51_PINS_H__ */
diff --git a/arch/arm/mach-mx51/pm.c b/arch/arm/mach-mx51/pm.c
deleted file mode 100644
index 86fc29a708a7..000000000000
--- a/arch/arm/mach-mx51/pm.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- *  Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-#include <linux/suspend.h>
-#include <linux/proc_fs.h>
-#include <linux/cpufreq.h>
-#include <linux/iram_alloc.h>
-#include <asm/cacheflush.h>
-#include <asm/tlb.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include "crm_regs.h"
-
-static struct cpu_wp *cpu_wp_tbl;
-static struct clk *cpu_clk;
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-static int org_freq;
-extern int cpufreq_suspended;
-extern int set_cpu_freq(int wp);
-#endif
-
-
-static struct device *pm_dev;
-struct clk *gpc_dvfs_clk;
-extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr);
-extern void cpu_cortexa8_do_idle(void *);
-extern struct cpu_wp *(*get_cpu_wp)(int *wp);
-
-extern int iram_ready;
-void *suspend_iram_base;
-void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL;
-
-static int mx51_suspend_enter(suspend_state_t state)
-{
-	void __iomem *sdclk_iomux_addr = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8);
-
-	if (gpc_dvfs_clk == NULL)
-		gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
-	/* gpc clock is needed for SRPG */
-	clk_enable(gpc_dvfs_clk);
-	switch (state) {
-	case PM_SUSPEND_MEM:
-		mxc_cpu_lp_set(STOP_POWER_OFF);
-		break;
-	case PM_SUSPEND_STANDBY:
-		mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if (tzic_enable_wake(0) != 0)
-		return -EAGAIN;
-
-	if (state == PM_SUSPEND_MEM) {
-		local_flush_tlb_all();
-		flush_cache_all();
-
-		/* Run the suspend code from iRAM. */
-		suspend_in_iram(sdclk_iomux_addr);
-
-		/*clear the EMPGC0/1 bits */
-		__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-		__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
-	} else {
-			cpu_do_idle();
-	}
-	clk_disable(gpc_dvfs_clk);
-
-	return 0;
-}
-
-/*
- * Called after processes are frozen, but before we shut down devices.
- */
-static int mx51_suspend_prepare(void)
-{
-#if defined(CONFIG_CPU_FREQ_IMX)
-	struct cpufreq_freqs freqs;
-	org_freq = clk_get_rate(cpu_clk);
-	freqs.old = org_freq / 1000;
-	freqs.new = cpu_wp_tbl[0].cpu_rate / 1000;
-	freqs.cpu = 0;
-	freqs.flags = 0;
-
-	cpufreq_suspended = 1;
-	if (clk_get_rate(cpu_clk) != cpu_wp_tbl[0].cpu_rate) {
-		set_cpu_freq(cpu_wp_tbl[0].cpu_rate);
-		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-	}
-#endif
-	return 0;
-}
-
-/*
- * Called before devices are re-setup.
- */
-static void mx51_suspend_finish(void)
-{
-#if defined(CONFIG_CPU_FREQ_IMX)
-	struct cpufreq_freqs freqs;
-
-	freqs.old = clk_get_rate(cpu_clk) / 1000;
-	freqs.new = org_freq / 1000;
-	freqs.cpu = 0;
-	freqs.flags = 0;
-
-	cpufreq_suspended = 0;
-
-	if (org_freq != clk_get_rate(cpu_clk)) {
-		set_cpu_freq(org_freq);
-		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-	}
-#endif
-}
-
-/*
- * Called after devices are re-setup, but before processes are thawed.
- */
-static void mx51_suspend_end(void)
-{
-}
-
-static int mx51_pm_valid(suspend_state_t state)
-{
-	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
-}
-
-struct platform_suspend_ops mx51_suspend_ops = {
-	.valid = mx51_pm_valid,
-	.prepare = mx51_suspend_prepare,
-	.enter = mx51_suspend_enter,
-	.finish = mx51_suspend_finish,
-	.end = mx51_suspend_end,
-};
-
-
-static int __devinit mx51_pm_probe(struct platform_device *pdev)
-{
-	pm_dev = &pdev->dev;
-	return 0;
-}
-
-static struct platform_driver mx51_pm_driver = {
-	.driver = {
-		   .name = "mx51_pm",
-		   },
-	.probe = mx51_pm_probe,
-};
-
-static int __init pm_init(void)
-{
-	int cpu_wp_nr;
-	unsigned long iram_paddr;
-
-	pr_info("Static Power Management for Freescale i.MX51\n");
-	if (platform_driver_register(&mx51_pm_driver) != 0) {
-		printk(KERN_ERR "mx51_pm_driver register failed\n");
-		return -ENODEV;
-	}
-	suspend_set_ops(&mx51_suspend_ops);
-	/* Move suspend routine into iRAM */
-	iram_alloc(SZ_4K, &iram_paddr);
-	/* Need to remap the area here since we want the memory region
-		 to be executable. */
-	suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
-					  MT_HIGH_VECTORS);
-	memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K);
-	suspend_in_iram = (void *)suspend_iram_base;
-
-	cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
-
-	cpu_clk = clk_get(NULL, "cpu_clk");
-	if (IS_ERR(cpu_clk)) {
-		printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__);
-		return PTR_ERR(cpu_clk);
-	}
-	printk(KERN_INFO "PM driver module loaded\n");
-
-	return 0;
-}
-
-
-static void __exit pm_cleanup(void)
-{
-	/* Unregister the device structure */
-	platform_driver_unregister(&mx51_pm_driver);
-}
-
-module_init(pm_init);
-module_exit(pm_cleanup);
-
-MODULE_AUTHOR("Freescale Semiconductor, Inc.");
-MODULE_DESCRIPTION("PM driver");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx51/serial.c b/arch/arm/mach-mx51/serial.c
deleted file mode 100644
index 83db40a0adbe..000000000000
--- a/arch/arm/mach-mx51/serial.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-/*!
- * @file mach-mx51/serial.c
- *
- * @brief This file contains the UART initiliazation.
- *
- * @ingroup MSL_MX51
- */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/mxc_uart.h>
-#include "serial.h"
-#include "board.h"
-
-#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
-
-/*!
- * This is an array where each element holds information about a UART port,
- * like base address of the UART, interrupt numbers etc. This structure is
- * passed to the serial_core.c file. Based on which UART is used, the core file
- * passes back the appropriate port structure as an argument to the control
- * functions.
- */
-static uart_mxc_port mxc_ports[] = {
-	[0] = {
-	       .port = {
-			.membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
-			.mapbase = UART1_BASE_ADDR,
-			.iotype = SERIAL_IO_MEM,
-			.irq = UART1_INT1,
-			.fifosize = 32,
-			.flags = ASYNC_BOOT_AUTOCONF,
-			.line = 0,
-			},
-	       .ints_muxed = UART1_MUX_INTS,
-	       .irqs = {UART1_INT2, UART1_INT3},
-	       .mode = UART1_MODE,
-	       .ir_mode = UART1_IR,
-	       .enabled = UART1_ENABLED,
-	       .hardware_flow = UART1_HW_FLOW,
-	       .cts_threshold = UART1_UCR4_CTSTL,
-	       .dma_enabled = UART1_DMA_ENABLE,
-	       .dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
-	       .rx_threshold = UART1_UFCR_RXTL,
-	       .tx_threshold = UART1_UFCR_TXTL,
-	       .dma_tx_id = MXC_DMA_UART1_TX,
-	       .dma_rx_id = MXC_DMA_UART1_RX,
-	       .rxd_mux = MXC_UART_RXDMUX,
-	       },
-	[1] = {
-	       .port = {
-			.membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
-			.mapbase = UART2_BASE_ADDR,
-			.iotype = SERIAL_IO_MEM,
-			.irq = UART2_INT1,
-			.fifosize = 32,
-			.flags = ASYNC_BOOT_AUTOCONF,
-			.line = 1,
-			},
-	       .ints_muxed = UART2_MUX_INTS,
-	       .irqs = {UART2_INT2, UART2_INT3},
-	       .mode = UART2_MODE,
-	       .ir_mode = UART2_IR,
-	       .enabled = UART2_ENABLED,
-	       .hardware_flow = UART2_HW_FLOW,
-	       .cts_threshold = UART2_UCR4_CTSTL,
-	       .dma_enabled = UART2_DMA_ENABLE,
-	       .dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
-	       .rx_threshold = UART2_UFCR_RXTL,
-	       .tx_threshold = UART2_UFCR_TXTL,
-	       .dma_tx_id = MXC_DMA_UART2_TX,
-	       .dma_rx_id = MXC_DMA_UART2_RX,
-	       .rxd_mux = MXC_UART_RXDMUX,
-	       },
-	[2] = {
-	       .port = {
-			.membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
-			.mapbase = UART3_BASE_ADDR,
-			.iotype = SERIAL_IO_MEM,
-			.irq = UART3_INT1,
-			.fifosize = 32,
-			.flags = ASYNC_BOOT_AUTOCONF,
-			.line = 2,
-			},
-	       .ints_muxed = UART3_MUX_INTS,
-	       .irqs = {UART3_INT2, UART3_INT3},
-	       .mode = UART3_MODE,
-	       .ir_mode = UART3_IR,
-	       .enabled = UART3_ENABLED,
-	       .hardware_flow = UART3_HW_FLOW,
-	       .cts_threshold = UART3_UCR4_CTSTL,
-	       .dma_enabled = UART3_DMA_ENABLE,
-	       .dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
-	       .rx_threshold = UART3_UFCR_RXTL,
-	       .tx_threshold = UART3_UFCR_TXTL,
-	       .dma_tx_id = MXC_DMA_UART3_TX,
-	       .dma_rx_id = MXC_DMA_UART3_RX,
-	       .rxd_mux = MXC_UART_RXDMUX,
-	       },
-};
-
-#if defined CONFIG_UART1_ENABLED
-static struct platform_device mxc_uart_device1 = {
-	.name = "mxcintuart",
-	.id = 0,
-	.dev = {
-		.platform_data = &mxc_ports[0],
-		},
-};
-#endif
-
-#if defined CONFIG_UART2_ENABLED
-static struct platform_device mxc_uart_device2 = {
-	.name = "mxcintuart",
-	.id = 1,
-	.dev = {
-		.platform_data = &mxc_ports[1],
-		},
-};
-#endif
-
-#if defined CONFIG_UART3_ENABLED
-static struct platform_device mxc_uart_device3 = {
-	.name = "mxcintuart",
-	.id = 2,
-	.dev = {
-		.platform_data = &mxc_ports[2],
-		},
-};
-#endif
-
-static int __init mxc_init_uart(void)
-{
-	/* Register all the MXC UART platform device structures */
-#if defined CONFIG_UART1_ENABLED
-	platform_device_register(&mxc_uart_device1);
-#endif
-#if defined CONFIG_UART2_ENABLED
-	platform_device_register(&mxc_uart_device2);
-#endif
-
-	/* Grab ownership of shared UARTs 3 and 4, only when enabled */
-#if defined CONFIG_UART3_ENABLED
-	platform_device_register(&mxc_uart_device3);
-#endif				/* UART3_ENABLED */
-	return 0;
-}
-
-#else
-static int __init mxc_init_uart(void)
-{
-	return 0;
-}
-#endif
-
-arch_initcall(mxc_init_uart);
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-axi_ahb0.h b/arch/arm/mach-stmp378x/include/mach/regs-axi_ahb0.h
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-axi_ahb0.h
+++ /dev/null