diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-02-19 14:01:35 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-12-24 01:27:32 +0100 |
| commit | 4fa0a0e7ddfed3b22b42d6b3e26246f11af59d59 (patch) | |
| tree | a4b0ae326eb613791b50352de2852b0d7c8c56b6 /arch/arm | |
| parent | 9edf41ddf86ed39736a5e74ffd522b178e68648b (diff) | |
ARM: imx: mach-imx7d: configure clock source per FEC instance
Configure Ethernet clock source for each FEC instance individually.
This allows to use different clock source setting for the two FEC
controllers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/mach-imx7d.c | 56 |
1 files changed, 33 insertions, 23 deletions
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index d9441898e756..7f9ea3c6dcd4 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -94,7 +94,7 @@ static void __init imx7d_enet_mdio_fixup(void) static void __init imx7d_enet_clk_sel(void) { - struct device_node *np; + struct device_node *np = NULL; struct clk *enet_out_clk; struct regmap *gpr; @@ -104,28 +104,38 @@ static void __init imx7d_enet_clk_sel(void) return; } - np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-fec"); - if (!np) { - pr_warn("%s: failed to find fec node\n", __func__); - return; - } - - enet_out_clk = of_clk_get_by_name(np, "enet_out"); - - if (IS_ERR(enet_out_clk)) { - pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); - /* use external clock for PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); - } else { - pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); - /* use internal clock generation and output it to PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); - clk_put(enet_out_clk); - } - - of_node_put(np); + do { + int id; + u32 clk_sel_mask, clk_dir_mask; + + np = of_find_compatible_node(np, NULL, "fsl,imx7d-fec"); + if (!np) + return; + + /* Determine controller ID by ethernet alias */ + id = of_alias_get_id(np, "ethernet"); + clk_sel_mask = id == 0 ? IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK : + IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK; + clk_dir_mask = id == 0 ? IMX7D_GPR1_ENET1_CLK_DIR_MASK : + IMX7D_GPR1_ENET2_CLK_DIR_MASK; + + enet_out_clk = of_clk_get_by_name(np, "enet_out"); + + if (IS_ERR(enet_out_clk)) { + pr_info("%s: fec%d: failed to get enet_out clock, assuming ext. clock source\n", + __func__, id + 1); + /* use external clock for PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, clk_sel_mask); + regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, 0); + } else { + pr_info("%s: fec%d: found enet_out clock, assuming internal clock source\n", + __func__, id + 1); + /* use internal clock generation and output it to PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, clk_dir_mask); + clk_put(enet_out_clk); + } + } while (np); } static inline void imx7d_enet_init(void) |