diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-06-10 12:29:13 +0530 |
|---|---|---|
| committer | Manish Tuteja <mtuteja@nvidia.com> | 2011-06-30 04:37:53 -0700 |
| commit | 9e3230dd71cc7521faeaa5abc09bc7dc476ec1e5 (patch) | |
| tree | 67c3107c44f572d23b65b4e11c218c0934138bc3 /arch/arm | |
| parent | c8990b1f0ab269292f25343191e79f86bff93c96 (diff) | |
ARM: tegra: clocks: Changed parent and init values
pll_m initialized to 0 so that it stays at the frequency configured
by BCT.
For AP25 pll_m runs at 760MHz. Peripherals connected to pll_m and
running at frequency not multiple of 760MHz switched to pll_c.
Bug 821534
Change-Id: I390b16a31194ad3efe79e68dfbcf371e225cfc70
Reviewed-on: http://git-master/r/36050
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler-baseband.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 10 |
3 files changed, 13 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/board-whistler-baseband.c b/arch/arm/mach-tegra/board-whistler-baseband.c index 25721965705e..3841492d92d1 100644 --- a/arch/arm/mach-tegra/board-whistler-baseband.c +++ b/arch/arm/mach-tegra/board-whistler-baseband.c @@ -28,20 +28,20 @@ MODULE_PARM_DESC(baseband_type, "baseband type"); static struct tegra_clk_init_table u3xx_clk[] = { /* spi slave controller clock @ 4 x 13 Mhz interface clock */ - { "sbc1", "pll_m", 52000000, true}, + { "sbc1", "pll_c", 52000000, true}, { NULL, NULL, 0, 0}, }; static struct tegra_clk_init_table n731_clk[] = { /* spi master controller clock @ 4 x 12 Mhz interface clock */ - { "sbc1", "pll_m", 48000000, true}, + { "sbc1", "pll_c", 48000000, true}, { NULL, NULL, 0, 0}, }; static struct tegra_clk_init_table spi_loopback_clk[] = { /* spi slave / master controller clocks @ 4 x max interface clock */ - { "sbc1", "pll_m", 60000000, true}, - { "sbc2", "pll_m", 60000000, true}, + { "sbc1", "pll_c", 60000000, true}, + { "sbc2", "pll_c", 60000000, true}, { NULL, NULL, 0, 0}, }; diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 4a12f93c9e3a..7aa74f19a78e 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -155,7 +155,7 @@ static struct tegra_ulpi_config ulpi_phy_config = { static __initdata struct tegra_clk_init_table whistler_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 216000000, true}, - { "uartc", "pll_m", 600000000, false}, + { "uartc", "pll_c", 600000000, false}, { "pwm", "clk_32k", 32768, false}, { "kbc", "clk_32k", 32768, true}, { "pll_a", NULL, 56448000, false}, diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 51aa082a45dd..d5d2d9c84ebb 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -100,13 +100,13 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* set up clocks that should always be on */ /* name parent rate enabled */ { "clk_m", NULL, 0, true }, - { "pll_m", "clk_m", 600000000, true }, + { "pll_m", "clk_m", 0, true }, { "pll_p", "clk_m", 216000000, true }, { "pll_p_out1", "pll_p", 28800000, true }, { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_m_out1", "pll_m", 120000000, true }, - { "sclk", "pll_m_out1", 120000000, true }, + { "sclk", "pll_c_out1", 120000000, true }, { "hclk", "sclk", 120000000, true }, { "pclk", "hclk", 60000000, true }, { "pll_x", NULL, 0, true }, @@ -123,6 +123,12 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sdmmc2", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, + { "mpe", "pll_c", 0, false}, + { "epp", "pll_c", 0, false}, + { "vi_sensor", "pll_c", 0, false}, + { "vi", "pll_c", 0, false}, + { "2d", "pll_c", 0, false}, + { "3d", "pll_c", 0, false}, { NULL, NULL, 0, 0}, }; |