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| author | Andre Przywara <andre.przywara@amd.com> | 2010-09-06 15:14:17 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-11-22 10:47:31 -0800 |
| commit | 7d778ac64b7d42ff3814348a25e99c778f8473f5 (patch) | |
| tree | fdfd102ccf36c51bae15da84ce61c24ad4098026 /arch/avr32 | |
| parent | 9809892e2ccb494ad97599a018788f5abe8f7842 (diff) | |
x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit
commit 7ef8aa72ab176e0288f363d1247079732c5d5792 upstream.
The AMD SSE5 feature set as-it has been replaced by some extensions
to the AVX instruction set. Thus the bit formerly advertised as SSE5
is re-used for one of these extensions (XOP).
Although this changes the /proc/cpuinfo output, it is not user visible, as
there are no CPUs (yet) having this feature.
To avoid confusion this should be added to the stable series, too.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
LKML-Reference: <1283778860-26843-2-git-send-email-andre.przywara@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/avr32')
0 files changed, 0 insertions, 0 deletions