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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-12 13:25:24 -0700 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-12 13:25:24 -0700 |
commit | 82afee684fe3badaf5ee3fc5b6fda687d558bfb5 (patch) | |
tree | 295abb35451a7eb1e46d6066e536e23d1a75668b /arch/blackfin/kernel/cacheinit.c | |
parent | 068345f4a873e8b0b511e8f94a595a20e176eeff (diff) | |
parent | f4d640c9be1979a603ed017e1e03a16ba3a4d7a1 (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (30 commits)
Blackfin serial driver: supporting BF548-EZKIT serial port
Video Console: Blackfin doesnt support VGA console
Blackfin arch: Add peripheral io API to gpio header file
Blackfin arch: set up gpio interrupt IRQ_PJ9 for BF54x ATAPI PATA driver
Blackfin arch: add missing CONFIG_LARGE_ALLOCS when upstream merging
Blackfin arch: as pointed out by Robert P. J. Day, update the CPU_FREQ name to match current Kconfig
Blackfin arch: extract the entry point from the linked kernel
Blackfin arch: clean up some coding style issues
Blackfin arch: combine the common code of free_initrd_mem and free_initmem
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation
Blackfin arch: use PAGE_SIZE when doing aligns rather than hardcoded values
Blackfin arch: fix bug set dma_address properly in dma_map_sg
Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default
Blackfin arch: Port the dm9000 driver to Blackfin by using the correct low-level io routines
Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch
Blackfin arch: scrub dead code
Blackfin arch: Fix Warning add some defines in BF54x header file
Blackfin arch: add BF54x missing GPIO access functions
Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS
Blackfin arch: Enable BF54x PIN/GPIO interrupts
...
Diffstat (limited to 'arch/blackfin/kernel/cacheinit.c')
-rw-r--r-- | arch/blackfin/kernel/cacheinit.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c new file mode 100644 index 000000000000..4d41a40e8133 --- /dev/null +++ b/arch/blackfin/kernel/cacheinit.c @@ -0,0 +1,66 @@ +/* + * Copyright 2004-2007 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/cpu.h> + +#include <asm/cacheflush.h> +#include <asm/blackfin.h> +#include <asm/cplbinit.h> + +#if defined(CONFIG_BLKFIN_CACHE) +void bfin_icache_init(void) +{ + unsigned long *table = icplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(ICPLB_ADDR0 + i * 4, addr); + bfin_write32(ICPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_IMEM_CONTROL(); + ctrl |= IMC | ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); +} +#endif + +#if defined(CONFIG_BLKFIN_DCACHE) +void bfin_dcache_init(void) +{ + unsigned long *table = dcplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(DCPLB_ADDR0 + i * 4, addr); + bfin_write32(DCPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_DMEM_CONTROL(); + ctrl |= DMEM_CNTR; + bfin_write_DMEM_CONTROL(ctrl); +} +#endif |