diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2008-05-17 16:38:52 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-05-17 16:38:52 +0800 |
| commit | 59069676383c6446f50555e04aed7f51d5de695e (patch) | |
| tree | ea0a34fda1ae463dad6f11f92773f515e4c1a34f /arch/blackfin | |
| parent | 86ad79321cbacdc4deebcde81849d19e26dd18e2 (diff) | |
Blackfin arch: IO Port functions to read/write unalligned memory
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/kernel/bfin_ksyms.c | 2 | ||||
| -rw-r--r-- | arch/blackfin/lib/ins.S | 21 | ||||
| -rw-r--r-- | arch/blackfin/lib/outs.S | 16 |
3 files changed, 35 insertions, 4 deletions
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index 053edff6c0d8..4367330909b2 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c @@ -90,7 +90,9 @@ EXPORT_SYMBOL(__umodsi3); EXPORT_SYMBOL(outsb); EXPORT_SYMBOL(insb); EXPORT_SYMBOL(outsw); +EXPORT_SYMBOL(outsw_8); EXPORT_SYMBOL(insw); +EXPORT_SYMBOL(insw_8); EXPORT_SYMBOL(outsl); EXPORT_SYMBOL(insl); EXPORT_SYMBOL(insl_16); diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index df7b8833a0c5..eba2343b1b59 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S @@ -7,7 +7,7 @@ * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops. * * Modified: - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> * * Bugs: Enter bugs at http://blackfin.uclinux.org/ @@ -63,6 +63,23 @@ ENTRY(_insw) RTS; ENDPROC(_insw) +ENTRY(_insw_8) + P0 = R0; /* P0 = port */ + cli R3; + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + SSYNC; + LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; +.Lword8_loop_s: R0 = W[P0]; + B[P1++] = R0; + R0 = R0 >> 8; + B[P1++] = R0; + NOP; +.Lword8_loop_e: NOP; + sti R3; + RTS; +ENDPROC(_insw_8) + ENTRY(_insb) P0 = R0; /* P0 = port */ cli R3; @@ -78,8 +95,6 @@ ENTRY(_insb) RTS; ENDPROC(_insb) - - ENTRY(_insl_16) P0 = R0; /* P0 = port */ cli R3; diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S index 4c3da8ae094e..3daf96035bf6 100644 --- a/arch/blackfin/lib/outs.S +++ b/arch/blackfin/lib/outs.S @@ -7,7 +7,7 @@ * Description: Implementation of outs{bwl} for BlackFin processors using zero overhead loops. * * Modified: Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -63,3 +63,17 @@ ENTRY(_outsb) .Lbyte_loop_e: B[P0] = R0; RTS; ENDPROC(_outsb) + +ENTRY(_outsw_8) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; +.Lword8_loop_s: R1 = B[P1++]; + R0 = B[P1++]; + R0 = R0 << 8; + R0 = R0 + R1; +.Lword8_loop_e: W[P0] = R0; + RTS; +ENDPROC(_outsw) |