diff options
| author | Jesper Nilsson <jespern@stork.se.axis.com> | 2007-11-29 17:11:23 +0100 |
|---|---|---|
| committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-02-08 11:06:23 +0100 |
| commit | 035e111f9a9b29843bc899f03d56f19d94bebb53 (patch) | |
| tree | cb46b3c0eb6d9f2cc915522153454d3acaa7fcda /arch/cris/arch-v32/mach-fs/hw_settings.S | |
| parent | 6107c61fd3e6b47106b078db1726ad814564efef (diff) | |
CRIS v32: Add new machine dependent files for Etrax-FS and Artpec-3.
The two chips are somewhat different, and needs different handling.
Adds handing of the dma, dram initialization, hardware settings, io,
memory arbiter and pinmux
Also moves the dma, dram initialization and io from CRIS v32 common files.
Diffstat (limited to 'arch/cris/arch-v32/mach-fs/hw_settings.S')
| -rw-r--r-- | arch/cris/arch-v32/mach-fs/hw_settings.S | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/cris/arch-v32/mach-fs/hw_settings.S b/arch/cris/arch-v32/mach-fs/hw_settings.S new file mode 100644 index 000000000000..8bde93c36214 --- /dev/null +++ b/arch/cris/arch-v32/mach-fs/hw_settings.S @@ -0,0 +1,70 @@ +/* + * This table is used by some tools to extract hardware parameters. + * The table should be included in the kernel and the decompressor. + * Don't forget to update the tools if you change this table. + * + * Copyright (C) 2001-2007 Axis Communications AB + * + * Authors: Mikael Starvik <starvik@axis.com> + */ + +#include <hwregs/asm/reg_map_asm.h> +#include <hwregs/asm/bif_core_defs_asm.h> +#include <hwregs/asm/gio_defs_asm.h> + + .ascii "HW_PARAM_MAGIC" ; Magic number + .dword 0xc0004000 ; Kernel start address + + ; Debug port +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + .dword 0 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + .dword 1 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + .dword 2 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + .dword 3 +#else + .dword 4 ; No debug +#endif + + ; Register values + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg) + .dword CONFIG_ETRAX_MEM_GRP1_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg) + .dword CONFIG_ETRAX_MEM_GRP2_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg) + .dword CONFIG_ETRAX_MEM_GRP3_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg) + .dword CONFIG_ETRAX_MEM_GRP4_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0) + .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1) + .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing) + .dword CONFIG_ETRAX_SDRAM_TIMING + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd) + .dword CONFIG_ETRAX_SDRAM_COMMAND + + .dword REG_ADDR(gio, regi_gio, rw_pa_dout) + .dword CONFIG_ETRAX_DEF_GIO_PA_OUT + .dword REG_ADDR(gio, regi_gio, rw_pa_oe) + .dword CONFIG_ETRAX_DEF_GIO_PA_OE + .dword REG_ADDR(gio, regi_gio, rw_pb_dout) + .dword CONFIG_ETRAX_DEF_GIO_PB_OUT + .dword REG_ADDR(gio, regi_gio, rw_pb_oe) + .dword CONFIG_ETRAX_DEF_GIO_PB_OE + .dword REG_ADDR(gio, regi_gio, rw_pc_dout) + .dword CONFIG_ETRAX_DEF_GIO_PC_OUT + .dword REG_ADDR(gio, regi_gio, rw_pc_oe) + .dword CONFIG_ETRAX_DEF_GIO_PC_OE + .dword REG_ADDR(gio, regi_gio, rw_pd_dout) + .dword CONFIG_ETRAX_DEF_GIO_PD_OUT + .dword REG_ADDR(gio, regi_gio, rw_pd_oe) + .dword CONFIG_ETRAX_DEF_GIO_PD_OE + .dword REG_ADDR(gio, regi_gio, rw_pe_dout) + .dword CONFIG_ETRAX_DEF_GIO_PE_OUT + .dword REG_ADDR(gio, regi_gio, rw_pe_oe) + .dword CONFIG_ETRAX_DEF_GIO_PE_OE + + .dword 0 ; No more register values |