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| author | Paul Mackerras <paulus@samba.org> | 2005-10-12 14:43:32 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2005-10-12 14:43:32 +1000 |
| commit | b6ec995a21a9428aef620b5adf46d047a18d88b8 (patch) | |
| tree | 6719121e6605cbca524b687f47336b9bbf3b8d41 /arch/i386/kernel/cpu/amd.c | |
| parent | 3a5f8c5f788d68e325d9fe3c26f4df5a5aee838a (diff) | |
| parent | da64c6ee6bb71bfb3f09d9bb89ce1aa4b1ee7e89 (diff) | |
Merge from Linus' tree
Diffstat (limited to 'arch/i386/kernel/cpu/amd.c')
| -rw-r--r-- | arch/i386/kernel/cpu/amd.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 73aeaf5a9d4e..53a1681cd964 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -28,6 +28,22 @@ static void __init init_amd(struct cpuinfo_x86 *c) int mbytes = num_physpages >> (20-PAGE_SHIFT); int r; +#ifdef CONFIG_SMP + unsigned long long value; + + /* Disable TLB flush filter by setting HWCR.FFDIS on K8 + * bit 6 of msr C001_0015 + * + * Errata 63 for SH-B3 steppings + * Errata 122 for all steppings (F+ have it disabled by default) + */ + if (c->x86 == 15) { + rdmsrl(MSR_K7_HWCR, value); + value |= 1 << 6; + wrmsrl(MSR_K7_HWCR, value); + } +#endif + /* * FIXME: We should handle the K5 here. Set up the write * range and also turn on MSR 83 bits 4 and 31 (write alloc, |