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authorTony Luck <tony.luck@intel.com>2006-03-21 08:21:26 -0800
committerTony Luck <tony.luck@intel.com>2006-03-21 08:21:26 -0800
commit409761bb6a06bd61e2d8e27a1af534371d9537ed (patch)
tree2c07068558092a01d70f737de9b9a34212a44d4b /arch/ia64/sn/kernel/sn2
parenta4e817ba24d2a52f0332c2ddcdbf77ddd6a92bbe (diff)
parente08e6c521355cd33e647b2f739885bc3050eead6 (diff)
Pull sn2-mmio-writes into release branch
Hand-fixed conflicts: include/asm-ia64/machvec_sn2.h Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn/kernel/sn2')
-rw-r--r--arch/ia64/sn/kernel/sn2/sn2_smp.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c
index b2e1e746b47f..d9d306c79f2d 100644
--- a/arch/ia64/sn/kernel/sn2/sn2_smp.c
+++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c
@@ -93,6 +93,27 @@ static inline unsigned long wait_piowc(void)
return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
}
+/**
+ * sn_migrate - SN-specific task migration actions
+ * @task: Task being migrated to new CPU
+ *
+ * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
+ * Context switching user threads which have memory-mapped MMIO may cause
+ * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
+ * from the previous CPU's Shub before execution resumes on the new CPU.
+ */
+void sn_migrate(struct task_struct *task)
+{
+ pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
+ volatile unsigned long *adr = last_pda->pio_write_status_addr;
+ unsigned long val = last_pda->pio_write_status_val;
+
+ /* Drain PIO writes from old CPU's Shub */
+ while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
+ != val))
+ cpu_relax();
+}
+
void sn_tlb_migrate_finish(struct mm_struct *mm)
{
/* flush_tlb_mm is inefficient if more than 1 users of mm */