[ARM/tegra] power: tuned cpu idle loop.

- Updated cpuidle driver parameters:
Determined LP2 state target_residency as a break even time balancing the
power cost of LP2 entry/exit (estimated via LP2 latency), and LP2_vs_LP3
power saving - this approach is consistent with governor interpretation
of residency. As a result the latency_to_residency factor reduced from
2.0 to 0.3.  Included exit latency into idle time returned to governor to
avoid double subtraction (by platform code and governor code) - otherwise
under-reporting of LP2 time would skew downward governor correction
algorithm. Replaced hard coded power good time with platform data.

- Updated DVFS parameters
Set CPU minimum frequency to 216MHz - additional dynamic power will be
compensated by savings due to increased LP2 residency (216MHz is provided
by low power PLL, and still allows CPU to run at lowest possible voltage).
Changed maximum CPU/EMC frequency ratio to match new low corner settings.

Change-Id: Ic58d0dd628f51bc3ede61a83c87792fca4f0845b
Reviewed-on: http://git-master/r/2916
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

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