Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...

1 files changed, 0 insertions, 161 deletions

diff --git a/arch/m32r/include/asm/m32r.h b/arch/m32r/include/asm/m32r.h
deleted file mode 100644
index d27f056d92f3..000000000000
--- a/arch/m32r/include/asm/m32r.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_M32R_H_
-#define _ASM_M32R_M32R_H_
-
-/*
- * Renesas M32R processor
- *
- * Copyright (C) 2003, 2004  Renesas Technology Corp.
- */
-
-
-/* Chip type */
-#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
-#include <asm/m32r_mp_fpga.h>
-#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
-	|| defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
-        || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#include <asm/m32102.h>
-#endif
-
-/* Platform type */
-#if defined(CONFIG_PLAT_M32700UT)
-#include <asm/m32700ut/m32700ut_pld.h>
-#include <asm/m32700ut/m32700ut_lan.h>
-#include <asm/m32700ut/m32700ut_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS	PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE	M32700UT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS	M32700UT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE	M32700UT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS	M32700UT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE	M32700UT_LCD_PLD_IRQ_BASE
-#endif  /* CONFIG_PLAT_M32700UT */
-
-#if defined(CONFIG_PLAT_OPSPUT)
-#include <asm/opsput/opsput_pld.h>
-#include <asm/opsput/opsput_lan.h>
-#include <asm/opsput/opsput_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS	PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE	OPSPUT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS	OPSPUT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE	OPSPUT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS	OPSPUT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE	OPSPUT_LCD_PLD_IRQ_BASE
-#endif  /* CONFIG_PLAT_OPSPUT */
-
-#if defined(CONFIG_PLAT_MAPPI2)
-#include <asm/mappi2/mappi2_pld.h>
-#endif	/* CONFIG_PLAT_MAPPI2 */
-
-#if defined(CONFIG_PLAT_MAPPI3)
-#include <asm/mappi3/mappi3_pld.h>
-#endif	/* CONFIG_PLAT_MAPPI3 */
-
-#if defined(CONFIG_PLAT_USRV)
-#include <asm/m32700ut/m32700ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS	PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE	M32700UT_PLD_IRQ_BASE
-#endif
-
-#if defined(CONFIG_PLAT_M32104UT)
-#include <asm/m32104ut/m32104ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS	PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE	M32104UT_PLD_IRQ_BASE
-#endif  /* CONFIG_PLAT_M32104 */
-
-/*
- * M32R Register
- */
-
-/*
- * MMU Register
- */
-
-#define MMU_REG_BASE	(0xffff0000)
-#define ITLB_BASE	(0xfe000000)
-#define DTLB_BASE	(0xfe000800)
-
-#define NR_TLB_ENTRIES	CONFIG_TLB_ENTRIES
-
-#define MATM	MMU_REG_BASE		/* MMU Address Translation Mode
-					   Register */
-#define MPSZ	(0x04 + MMU_REG_BASE)	/* MMU Page Size Designation Register */
-#define MASID	(0x08 + MMU_REG_BASE)	/* MMU Address Space ID Register */
-#define MESTS	(0x0c + MMU_REG_BASE)	/* MMU Exception Status Register */
-#define MDEVA	(0x10 + MMU_REG_BASE)	/* MMU Operand Exception Virtual
-					   Address Register */
-#define MDEVP	(0x14 + MMU_REG_BASE)	/* MMU Operand Exception Virtual Page
-					   Number Register */
-#define MPTB	(0x18 + MMU_REG_BASE)	/* MMU Page Table Base Register */
-#define MSVA	(0x20 + MMU_REG_BASE)	/* MMU Search Virtual Address
-					   Register */
-#define MTOP	(0x24 + MMU_REG_BASE)	/* MMU TLB Operation Register */
-#define MIDXI	(0x28 + MMU_REG_BASE)	/* MMU Index Register for
-					   Instruciton */
-#define MIDXD	(0x2c + MMU_REG_BASE)	/* MMU Index Register for Operand */
-
-#define MATM_offset	(MATM - MMU_REG_BASE)
-#define MPSZ_offset	(MPSZ - MMU_REG_BASE)
-#define MASID_offset	(MASID - MMU_REG_BASE)
-#define MESTS_offset	(MESTS - MMU_REG_BASE)
-#define MDEVA_offset	(MDEVA - MMU_REG_BASE)
-#define MDEVP_offset	(MDEVP - MMU_REG_BASE)
-#define MPTB_offset	(MPTB - MMU_REG_BASE)
-#define MSVA_offset	(MSVA - MMU_REG_BASE)
-#define MTOP_offset	(MTOP - MMU_REG_BASE)
-#define MIDXI_offset	(MIDXI - MMU_REG_BASE)
-#define MIDXD_offset	(MIDXD - MMU_REG_BASE)
-
-#define MESTS_IT	(1 << 0)	/* Instruction TLB miss */
-#define MESTS_IA	(1 << 1)	/* Instruction Access Exception */
-#define MESTS_DT	(1 << 4)	/* Operand TLB miss */
-#define MESTS_DA	(1 << 5)	/* Operand Access Exception */
-#define MESTS_DRW	(1 << 6)	/* Operand Write Exception Flag */
-
-/*
- * PSW (Processor Status Word)
- */
-
-/* PSW bit */
-#define M32R_PSW_BIT_SM   (7)    /* Stack Mode */
-#define M32R_PSW_BIT_IE   (6)    /* Interrupt Enable */
-#define M32R_PSW_BIT_PM   (3)    /* Processor Mode [0:Supervisor,1:User] */
-#define M32R_PSW_BIT_C    (0)    /* Condition */
-#define M32R_PSW_BIT_BSM  (7+8)  /* Backup Stack Mode */
-#define M32R_PSW_BIT_BIE  (6+8)  /* Backup Interrupt Enable */
-#define M32R_PSW_BIT_BPM  (3+8)  /* Backup Processor Mode */
-#define M32R_PSW_BIT_BC   (0+8)  /* Backup Condition */
-
-/* PSW bit map */
-#define M32R_PSW_SM   (1UL<< M32R_PSW_BIT_SM)   /* Stack Mode */
-#define M32R_PSW_IE   (1UL<< M32R_PSW_BIT_IE)   /* Interrupt Enable */
-#define M32R_PSW_PM   (1UL<< M32R_PSW_BIT_PM)   /* Processor Mode */
-#define M32R_PSW_C    (1UL<< M32R_PSW_BIT_C)    /* Condition */
-#define M32R_PSW_BSM  (1UL<< M32R_PSW_BIT_BSM)  /* Backup Stack Mode */
-#define M32R_PSW_BIE  (1UL<< M32R_PSW_BIT_BIE)  /* Backup Interrupt Enable */
-#define M32R_PSW_BPM  (1UL<< M32R_PSW_BIT_BPM)  /* Backup Processor Mode */
-#define M32R_PSW_BC   (1UL<< M32R_PSW_BIT_BC)   /* Backup Condition */
-
-/*
- * Direct address to SFR
- */
-
-#include <asm/page.h>
-#ifdef CONFIG_MMU
-#define NONCACHE_OFFSET  (__PAGE_OFFSET + 0x20000000)
-#else
-#define NONCACHE_OFFSET  __PAGE_OFFSET
-#endif /* CONFIG_MMU */
-
-#define M32R_ICU_ISTS_ADDR  M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IPICR_ADDR  M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IMASK_ADDR  M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_CPU_NAME_ADDR  M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_MODEL_ID_ADDR  M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_VERSION_ADDR   M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
-
-#endif /* _ASM_M32R_M32R_H_ */