diff options
author | Greg Ungerer <gerg@uclinux.org> | 2012-07-15 21:55:01 +1000 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 23:33:47 +1000 |
commit | e1e362dc074c2981e7f78d26bf38a4f14be52ecd (patch) | |
tree | 04a5e228b586561c274d1267b907f5b062ee0018 /arch/m68k/include/asm/m5206sim.h | |
parent | 6a3a786d02172b34d0ffba6f80bd1150da51125d (diff) |
m68knommu: make ColdFire SYPCR and RSR register definitions absolute addresses
Make all definitions of the ColdFire Reset and System registers absolute
addresses. Currently some are relative to the MBAR peripheral region.
The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the abolsute
address - factoring out whether it is an offset into a peripheral region.
This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5206sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index e8bae33aed60..d67ce08e508d 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -43,8 +43,8 @@ #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ -#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ |