Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu arch updates from Greg Ungerer:
 "Most of it is a cleanup of the ColdFire hardware header files.  We
  have had a few occurrances of bugs caused by inconsistent definitions
  of peripheral addresses.  These patches make them all consistent, and
  also clean out a bunch of old crap.  Overall we remove about 1000
  lines."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits)
  m68knommu: fix inconsistent formating in ColdFire 5407 definitions
  m68knommu: fix inconsistent formating in ColdFire 5307 definitions
  m68knommu: fix inconsistent formating in ColdFire 527x definitions
  m68knommu: fix inconsistent formating in ColdFire 5272 definitions
  m68knommu: fix inconsistent formating in ColdFire 523x definitions
  m68knommu: clean up ColdFire 54xx General Timer definitions
  m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU
  m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x
  m68knommu: move ColdFire slice timer address defiens to 54xx header
  m68knommu: use read/write IO access functions in ColdFire m532x setup code
  m68knommu: modify ColdFire 532x GPIO register definitions to be consistent
  m68knommu: remove a lot of unsed definitions for 532x ColdFire
  m68knommu: use definitions for the ColdFire 528x FEC multi-function pins
  m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
  m68knommu: remove unused ColdFire 5282 register definitions
  m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins
  m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses
  m68knommu: make remaining ColdFire 5272 register definitions absolute addresses
  m68knommu: make ColdFire Park and Assignment register definitions absolute addresses
  m68knommu: make ColdFire Chip Select register definitions absolute addresses
  ...

1 files changed, 50 insertions, 34 deletions

diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa5104d3d6..1bebbe78055a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,19 +184,33 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR			MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR			MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR			MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR			MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR			MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR		MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR		MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR		MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR		MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR		MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX			100
-#define MCFGPIO_IRQ_MAX			8
-#define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX		100
+#define MCFGPIO_IRQ_MAX		8
+#define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK	0x000f
+#define UART1_ENABLE_MASK	0x0ff0
+#define UART2_ENABLE_MASK	0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100004)
@@ -279,18 +293,36 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR			MCFGPIO_PODR_BUSCTL
-#define MCFGPIO_PDDR			MCFGPIO_PDDR_BUSCTL
-#define MCFGPIO_PPDR			MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_SETR			MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_CLRR			MCFGPIO_PCLRR_BUSCTL
+#define MCFGPIO_PODR		MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR		MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR		MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR		MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR		MCFGPIO_PCLRR_BUSCTL
 
-#define MCFGPIO_PIN_MAX			148
-#define MCFGPIO_IRQ_MAX			8
-#define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX		148
+#define MCFGPIO_IRQ_MAX		8
+#define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB		(MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL	(MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL	(MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK	0x000f
+#define UART1_ENABLE_MASK	0x00f0
+#define UART2_ENABLE_MASK	0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -311,22 +343,6 @@
 #define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
 
 /*
- *	GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART	0x100048	/* PAR UART address */
-#define UART0_ENABLE_MASK	0x000f
-#define UART1_ENABLE_MASK	0x0ff0
-#define UART2_ENABLE_MASK	0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART	0x10007c	/* PAR UART address */
-#define UART0_ENABLE_MASK	0x000f
-#define UART1_ENABLE_MASK	0x00f0
-#define UART2_ENABLE_MASK	0x3f00 
-#endif
-
-/*
  *  Reset Control Unit (relative to IPSBAR).
  */
 #define	MCF_RCR			(MCF_IPSBAR + 0x110000)