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authorGreg Ungerer <gerg@uclinux.org>2011-03-05 23:50:37 +1000
committerGreg Ungerer <gerg@uclinux.org>2011-03-15 21:01:54 +1000
commit571f0608e1a53d6d405c385cc9c11b7902b35b7f (patch)
tree07642ba4284f7287bdeb5b8abaaf987ed5fb9f1b /arch/m68knommu/platform/coldfire/head.S
parentf317c71a2f3dcdae26055e6dd390d06c5efe5795 (diff)
m68knommu: remove MBAR and IPSBAR hacks for the ColdFire 520x CPUs
The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses. They do not use the setable peripheral address registers like the MBAR and IPSBAR used on many other ColdFire parts. Don't use fake values of MBAR and IPSBAR when using peripheral addresses for them, there is no need to. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/coldfire/head.S')
-rw-r--r--arch/m68knommu/platform/coldfire/head.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index d5977909ae5f..7967e8ab9fae 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -68,14 +68,14 @@
#elif defined(CONFIG_M520x)
.macro GET_MEM_SIZE
clrl %d0
- movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
+ movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
andl #0x1f, %d2 /* Get only the chip select size */
beq 3f /* Check if it is enabled */
addql #1, %d2 /* Form exponent */
moveql #1, %d0
lsll %d2, %d0 /* 2 ^ exponent */
3:
- movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
+ movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
andl #0x1f, %d2 /* Get only the chip select size */
beq 4f /* Check if it is enabled */
addql #1, %d2 /* Form exponent */