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authorJames Hogan <james.hogan@imgtec.com>2013-03-07 17:20:53 +0000
committerJames Hogan <james.hogan@imgtec.com>2013-03-15 13:21:17 +0000
commit9e7129630329d50b8e8c3403bb71c85a7c3cbe35 (patch)
treef925f533798f07d975abebb2c27df4380ad12afd /arch/metag/include
parent00e6c92304ce38ff48029471c929d31a25e5cf10 (diff)
metag: smp: copy cache partition and enable GCOn
When starting an SMP hardware thread, copy the cache partition configuration so that the threads share the same cache partitions. Also enable the GCOn bit if running in the local half of the virtual address space to enable coherency of shared local cache partitions. An atomic unlock system event is executed by the new cpu before any memory is read to ensure that any writes made by the boot cpu prior to full coherency taking effect are visible to the new cpu. This is to allow SMP to work even when the bootloader hasn't configured the caches for coherency. A log message is printed to describe the cache partition changes so that the user is aware of potential unintentional cache wastage if they've configured the cache partitions in the wrong way. Signed-off-by: James Hogan <james.hogan@imgtec.com>
Diffstat (limited to 'arch/metag/include')
-rw-r--r--arch/metag/include/asm/metag_mem.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/metag/include/asm/metag_mem.h b/arch/metag/include/asm/metag_mem.h
index 3f7b54d8ccac..aa5a076df439 100644
--- a/arch/metag/include/asm/metag_mem.h
+++ b/arch/metag/include/asm/metag_mem.h
@@ -700,6 +700,9 @@
#define SYSC_xCPARTG_AND_S 8
#define SYSC_xCPARTL_OR_BITS 0x000F0000 /* Ors into top 4 bits */
#define SYSC_xCPARTL_OR_S 16
+#ifdef METAC_2_1
+#define SYSC_DCPART_GCON_BIT 0x00100000 /* Coherent shared local */
+#endif /* METAC_2_1 */
#define SYSC_xCPARTG_OR_BITS 0x0F000000 /* Ors into top 4 bits */
#define SYSC_xCPARTG_OR_S 24
#define SYSC_CWRMODE_BIT 0x80000000 /* Write cache mode bit */