diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-02-21 12:51:33 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2013-02-21 12:51:33 +0100 |
commit | 8bfc245f9ad7bd4e461179e4e7852ef99b8b6144 (patch) | |
tree | 0ad091f645fbc8318634599d278966a53d3922ee /arch/mips/ath79/gpio.c | |
parent | 612663a974065c3445e641d046769fe4c55a6438 (diff) | |
parent | 535237cecab2b078114be712c67e89a0db61965f (diff) |
Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
Diffstat (limited to 'arch/mips/ath79/gpio.c')
-rw-r--r-- | arch/mips/ath79/gpio.c | 52 |
1 files changed, 25 insertions, 27 deletions
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index 48fe762d2526..8d025b028bb1 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -137,49 +137,45 @@ static struct gpio_chip ath79_gpio_chip = { .base = 0, }; -void ath79_gpio_function_enable(u32 mask) +static void __iomem *ath79_gpio_get_function_reg(void) { - void __iomem *base = ath79_gpio_base; - unsigned long flags; + u32 reg = 0; - spin_lock_irqsave(&ath79_gpio_lock, flags); - - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, - base + AR71XX_GPIO_REG_FUNC); - /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; + else if (soc_is_ar934x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); - spin_unlock_irqrestore(&ath79_gpio_lock, flags); + return ath79_gpio_base + reg; } -void ath79_gpio_function_disable(u32 mask) +void ath79_gpio_function_setup(u32 set, u32 clear) { - void __iomem *base = ath79_gpio_base; + void __iomem *reg = ath79_gpio_get_function_reg(); unsigned long flags; spin_lock_irqsave(&ath79_gpio_lock, flags); - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, - base + AR71XX_GPIO_REG_FUNC); + __raw_writel((__raw_readl(reg) & ~clear) | set, reg); /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + __raw_readl(reg); spin_unlock_irqrestore(&ath79_gpio_lock, flags); } -void ath79_gpio_function_setup(u32 set, u32 clear) +void ath79_gpio_function_enable(u32 mask) { - void __iomem *base = ath79_gpio_base; - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, - base + AR71XX_GPIO_REG_FUNC); - /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + ath79_gpio_function_setup(mask, 0); +} - spin_unlock_irqrestore(&ath79_gpio_lock, flags); +void ath79_gpio_function_disable(u32 mask) +{ + ath79_gpio_function_setup(0, mask); } void __init ath79_gpio_init(void) @@ -198,12 +194,14 @@ void __init ath79_gpio_init(void) ath79_gpio_count = AR933X_GPIO_COUNT; else if (soc_is_ar934x()) ath79_gpio_count = AR934X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; else BUG(); ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ath79_gpio_chip.ngpio = ath79_gpio_count; - if (soc_is_ar934x()) { + if (soc_is_ar934x() || soc_is_qca955x()) { ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; } |