diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2010-02-26 19:04:15 +0000 |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2010-02-26 19:06:24 +0000 |
commit | a7790532f5b7358c33a6b1834dc2b318de209f31 (patch) | |
tree | 0ceb9e24b3f54cb5c8453fb5a218e2a94a0f1cce /arch/mips/bcm47xx/prom.c | |
parent | 2764fb4244cc1bc08df3667924ca4a972e90ac70 (diff) | |
parent | 60b341b778cc2929df16c0a504c91621b3c6a4ad (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
The SmartMedia FTL code depends on new kfifo bits from 2.6.33
Diffstat (limited to 'arch/mips/bcm47xx/prom.c')
-rw-r--r-- | arch/mips/bcm47xx/prom.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index fb284c3b2cff..29d3cbf9555f 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -100,11 +100,11 @@ static __init void prom_init_console(void) static __init void prom_init_cmdline(void) { - static char buf[CL_SIZE] __initdata; + static char buf[COMMAND_LINE_SIZE] __initdata; /* Get the kernel command line from CFE */ - if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { - buf[CL_SIZE-1] = 0; + if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) { + buf[COMMAND_LINE_SIZE - 1] = 0; strcpy(arcs_cmdline, buf); } @@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void) * as CFE is not available anymore later in the boot process. */ if ((strstr(arcs_cmdline, "console=")) == NULL) { /* Try to read the default serial port used by CFE */ - if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0) + if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0) || (strncmp("uart", buf, 4))) /* Default to uart0 */ strcpy(buf, "uart0"); /* Compute the new command line */ - snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200", + snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200", arcs_cmdline, buf[4]); } } @@ -141,6 +141,14 @@ static __init void prom_init_mem(void) break; } + /* Ignoring the last page when ddr size is 128M. Cached + * accesses to last page is causing the processor to prefetch + * using address above 128M stepping out of the ddr address + * space. + */ + if (mem == 0x8000000) + mem -= 0x1000; + add_memory_region(0, mem, BOOT_MEM_RAM); } |