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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-11-14 16:12:23 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-22 20:18:58 +0100
commit1745c1ef88c095a99c95d13b275774d18774465d (patch)
tree9ea07338f8852f3a6db815e8ce945023c99248ad /arch/mips/include/asm/cpu-features.h
parentc01905eeee579db98dd6b39d3f41497065ecc273 (diff)
MIPS: features: Add initial support for TLBINVF capable cores
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6130/
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
-rw-r--r--arch/mips/include/asm/cpu-features.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index d445d060e346..296606b19186 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -20,6 +20,9 @@
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
+#ifndef cpu_has_tlbinv
+#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
+#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that