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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-12 16:25:35 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-12 16:25:35 -0800 |
| commit | 9219a3b9889dbc7dae68e472f239672ff48860b0 (patch) | |
| tree | c6446d63dd7ffb0f118804e354eee3d80041717e /arch/mips/include/asm/mach-cavium-octeon/war.h | |
| parent | 23ead7291269db3be71b442324381c8d63e5d0b3 (diff) | |
| parent | cde15b5927fea3e1b4de0b277008cf273d8b000b (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (37 commits)
MIPS: Only write c0_framemask on CPUs which have this register.
MIPS: Alchemy: new userspace suspend interface for development boards.
MIPS: Alchemy: dbdma suspend/resume support.
MIPS: Alchemy: Fix up PM code on Au1550/Au1200
MIPS: Alchemy: move calc_clock function.
MIPS: Alchemy: RTC counter clocksource / clockevent support.
MIPS: make cp0 counter clocksource/event usable as fallback.
MIPS: Alchemy: remove cpu_table.
MIPS: Alchemy: remove get/set_au1x00_lcd_clock().
MIPS: Print irq handler description
MIPS: Alchemy: pb1200: update CPLD cascade irq handler.
MIPS: Alchemy: update core interrupt code.
MIPS: Alchemy: move commandline mangling out of common code
MIPS: Alchemy: devboards: consolidate files
MIPS: Alchemy: Move development board code to common subdirectory
MIPS: Add Cavium OCTEON to arch/mips/Kconfig
MIPS: Add defconfig for Cavium OCTEON.
MIPS: Adjust the dma-common.c platform hooks.
MIPS: Add Cavium OCTEON slot into proper tlb category.
MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.
...
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon/war.h')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/war.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h new file mode 100644 index 000000000000..c4712d7cc81d --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com> + */ +#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H +#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */ |