diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2014-06-04 22:53:02 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-06-04 22:53:02 +0200 |
| commit | f8647b506d7116a1a3accd8d618184096e85f50b (patch) | |
| tree | f10bc7201fda2a36c035548a0ea62210ad57adb6 /arch/mips/include/asm | |
| parent | 1d421ca9d7edbac1eb118631ee039d50ab54771e (diff) | |
| parent | f7a89f1b8eb598ac5da61c9795b3d847baa73d12 (diff) | |
Merge branch '3.15-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/cpu-info.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/msa.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 7ba0e07a9091..47d5967ce7ef 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -39,14 +39,14 @@ struct cache_desc { #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ struct cpuinfo_mips { - unsigned int udelay_val; - unsigned int asid_cache; + unsigned long asid_cache; /* * Capability and feature descriptor structure for MIPS CPU */ unsigned long options; unsigned long ases; + unsigned int udelay_val; unsigned int processor_id; unsigned int fpu_id; unsigned int msa_id; diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index 52450a040f44..538f6d482db8 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -84,7 +84,7 @@ static inline void write_msa_##name(unsigned int val) \ __asm__ __volatile__( \ " .set push\n" \ " .set msa\n" \ - " cfcmsa $" #cs ", %0\n" \ + " ctcmsa $" #cs ", %0\n" \ " .set pop\n" \ : : "r"(val)); \ } |