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| author | Ingo Molnar <mingo@elte.hu> | 2008-07-14 10:31:59 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-14 10:31:59 +0200 |
| commit | b4ba0ba24b57ec975482f4ba2d350fbee7557240 (patch) | |
| tree | c076e4c4e446180d6a36df3d55ae2ba7b0d7736e /arch/mips/kernel/cevt-txx9.c | |
| parent | a033c332e047397904ed74816946b2edd9b0d5cd (diff) | |
| parent | bce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff) | |
Merge commit 'v2.6.26' into core/locking
Diffstat (limited to 'arch/mips/kernel/cevt-txx9.c')
| -rw-r--r-- | arch/mips/kernel/cevt-txx9.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 795cb8fb0d74..b5fc4eb412d2 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr) struct txx9_tmr_reg __iomem *tmrptr; tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); + /* Start once to make CounterResetEnable effective */ + __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); + /* Stop and reset the counter */ __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); __raw_writel(0, &tmrptr->tisr); __raw_writel(0xffffffff, &tmrptr->cpra); |