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authorDavid Daney <ddaney@caviumnetworks.com>2009-01-05 15:29:58 -0800
committerRalf Baechle <ralf@linux-mips.org>2009-01-30 21:32:58 +0000
commit8bc6d05b481aa7dc79c81b8ffac0da755e149643 (patch)
tree0c6b7c62dbec9d598546c7e58cb13c0c78212a1e /arch/mips/kernel/genex.S
parent7adbedaf4469dcdcd6a1ab9bdeb8ad854d4f9827 (diff)
MIPS: Read watch registers with interrupts disabled.
If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/genex.S')
-rw-r--r--arch/mips/kernel/genex.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index fb6f73148df2..8882e5766f27 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
BUILD_HANDLER fpe fpe fpe silent /* #15 */
BUILD_HANDLER mdmx mdmx sti silent /* #22 */
#ifdef CONFIG_HARDWARE_WATCHPOINTS
- BUILD_HANDLER watch watch sti silent /* #23 */
+ /*
+ * For watch, interrupts will be enabled after the watch
+ * registers are read.
+ */
+ BUILD_HANDLER watch watch cli silent /* #23 */
#else
BUILD_HANDLER watch watch sti verbose /* #23 */
#endif