diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-02-03 23:06:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:24 +0100 |
| commit | 925ddb04c5eee5668e7229c71580d458ed61eb9b (patch) | |
| tree | f4a7cbd9047284edbf95235d02e03edf57a9a259 /arch/mips/kernel/irq_cpu.c | |
| parent | 38b18f72587422450bd01695b471b3ae2ff4b169 (diff) | |
Mask and ack CPU interrupts upon initialization. Keep the state
of software interrupts when unmasking.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq_cpu.c')
| -rw-r--r-- | arch/mips/kernel/irq_cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 2b936cf1ef70..8f8c15fa748d 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -3,6 +3,8 @@ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> * * This file define the irq handler for MIPS CPU interrupts. * @@ -37,7 +39,6 @@ static int mips_cpu_irq_base; static inline void unmask_mips_irq(unsigned int irq) { - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); set_c0_status(0x100 << (irq - mips_cpu_irq_base)); } @@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base) { int i; + /* Mask interrupts. */ + clear_c0_status(ST0_IM); + clear_c0_cause(CAUSEF_IP); + for (i = irq_base; i < irq_base + 8; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = NULL; |