Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr

Pull MIPS updates from Ralf Baechle:
 - Support for Imgtec's Aptiv family of MIPS cores.
 - Improved detection of BCM47xx configurations.
 - Fix hiberation for certain configurations.
 - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
   systems.
 - Detection and support for the MIPS P5600 core.
 - A few more random fixes that didn't make 3.14.
 - Support for the EVA Extended Virtual Addressing
 - Switch Alchemy to the platform PATA driver
 - Complete unification of Alchemy support
 - Allow availability of I/O cache coherency to be runtime detected
 - Improvments to multiprocessing support for Imgtec platforms
 - A few microoptimizations
 - Cleanups of FPU support
 - Paul Gortmaker's fixes for the init stuff
 - Support for seccomp

* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
  MIPS: CPC: Use __raw_ memory access functions
  MIPS: CM: use __raw_ memory access functions
  MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
  MIPS: Malta: GIC IPIs may be used without MT
  MIPS: smp-mt: Use common GIC IPI implementation
  MIPS: smp-cmp: Remove incorrect core number probe
  MIPS: Fix gigaton of warning building with microMIPS.
  MIPS: Fix core number detection for MT cores
  MIPS: MT: core_nvpes function to retrieve VPE count
  MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
  MIPS: Lasat: Replace del_timer by del_timer_sync
  MIPS: Malta: Setup PM I/O region on boot
  MIPS: Loongson: Add a Loongson-3 default config file
  MIPS: Loongson 3: Add CPU hotplug support
  MIPS: Loongson 3: Add Loongson-3 SMP support
  MIPS: Loongson: Add Loongson-3 Kconfig options
  MIPS: Loongson: Add swiotlb to support All-Memory DMA
  MIPS: Loongson 3: Add serial port support
  MIPS: Loongson 3: Add IRQ init and dispatch support
  MIPS: Loongson 3: Add HT-linked PCI support
  ...

1 files changed, 52 insertions, 0 deletions

diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
new file mode 100644
index 000000000000..c9dc67402969
--- /dev/null
+++ b/arch/mips/kernel/mips-cpc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/errno.h>
+
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+
+void __iomem *mips_cpc_base;
+
+phys_t __weak mips_cpc_phys_base(void)
+{
+	u32 cpc_base;
+
+	if (!mips_cm_present())
+		return 0;
+
+	if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
+		return 0;
+
+	/* If the CPC is already enabled, leave it so */
+	cpc_base = read_gcr_cpc_base();
+	if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
+		return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
+
+	/* Otherwise, give it the default address & enable it */
+	cpc_base = mips_cpc_default_phys_base();
+	write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
+	return cpc_base;
+}
+
+int mips_cpc_probe(void)
+{
+	phys_t addr;
+
+	addr = mips_cpc_phys_base();
+	if (!addr)
+		return -ENODEV;
+
+	mips_cpc_base = ioremap_nocache(addr, 0x8000);
+	if (!mips_cpc_base)
+		return -ENXIO;
+
+	return 0;
+}