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| author | Al Viro <viro@zeniv.linux.org.uk> | 2016-05-11 00:00:29 -0400 |
|---|---|---|
| committer | Al Viro <viro@zeniv.linux.org.uk> | 2016-05-11 00:00:29 -0400 |
| commit | e4d35be584be88a3db3fa5635a97c62a2ec5aafe (patch) | |
| tree | fc22a7fb65697306edd71411959ccee6df60c64d /arch/mips/kernel/pm-cps.c | |
| parent | 99d825822eade8d827a1817357cbf3f889a552d6 (diff) | |
| parent | 38b78a5f18584db6fa7441e0f4531b283b0e6725 (diff) | |
Merge branch 'ovl-fixes' into for-linus
Diffstat (limited to 'arch/mips/kernel/pm-cps.c')
| -rw-r--r-- | arch/mips/kernel/pm-cps.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index f63a289977cc..fa3f9ebad8f4 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) /* * Disable all but self interventions. The load from COHCTL is defined * by the interAptiv & proAptiv SUMs as ensuring that the operation - * resulting from the preceeding store is complete. + * resulting from the preceding store is complete. */ uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core); uasm_i_sw(&p, t0, 0, r_pcohctl); |