diff options
| author | Chris Dearman <chris@mips.com> | 2007-04-27 15:58:41 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-06-14 18:25:14 +0100 |
| commit | b72c05262298cc2ac92edb657f5ea3a97ad5ea3d (patch) | |
| tree | 41819862465a5cd6b89eb7b8bff3a79a5817064f /arch/mips/mips-boards/generic/init.c | |
| parent | eedab661a51966c454e38c17266a531aa58b4a98 (diff) | |
[MIPS] Malta: Fix for SOCitSC based Maltas
And an attempt to tidy up the core/controller differences.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/generic/init.c')
| -rw-r--r-- | arch/mips/mips-boards/generic/init.c | 62 |
1 files changed, 44 insertions, 18 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 88e9c2a7a2f9..4eabc1eadd23 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -57,7 +57,8 @@ int *_prom_argv, *_prom_envp; int init_debug = 0; -unsigned int mips_revision_corid; +int mips_revision_corid; +int mips_revision_sconid; /* Bonito64 system controller register base. */ unsigned long _pcictrl_bonito; @@ -275,13 +276,38 @@ void __init prom_init(void) else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } - switch(mips_revision_corid) { + + mips_revision_sconid = MIPS_REVISION_SCONID; + if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: + mips_revision_sconid = MIPS_REVISION_SCON_GT64120; + break; + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + mips_revision_sconid = MIPS_REVISION_SCON_BONITO; + break; + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; + break; + default: + mips_display_message("CC Error"); + while (1); /* We die here... */ + } + } + + switch (mips_revision_sconid) { u32 start, map, mask, data; - case MIPS_REVISION_CORID_QED_RM5261: - case MIPS_REVISION_CORID_CORE_LV: - case MIPS_REVISION_CORID_CORE_FPGA: - case MIPS_REVISION_CORID_CORE_FPGAR2: + case MIPS_REVISION_SCON_GT64120: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. @@ -305,9 +331,7 @@ void __init prom_init(void) set_io_port_base(MALTA_GT_PORT_BASE); break; - case MIPS_REVISION_CORID_CORE_EMUL_BON: - case MIPS_REVISION_CORID_BONITO64: - case MIPS_REVISION_CORID_CORE_20K: + case MIPS_REVISION_SCON_BONITO: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* @@ -334,13 +358,10 @@ void __init prom_init(void) set_io_port_base(MALTA_BONITO_PORT_BASE); break; - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - + mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -374,10 +395,15 @@ void __init prom_init(void) set_io_port_base(MALTA_MSC_PORT_BASE); break; + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); + goto mips_pci_controller; + default: - /* Unknown Core card */ - mips_display_message("CC Error"); - while(1); /* We die here... */ + /* Unknown system controller */ + mips_display_message("SC Error"); + while (1); /* We die here... */ } #endif board_nmi_handler_setup = mips_nmi_setup; |