diff options
| author | Chris Dearman <chris@mips.com> | 2007-05-29 20:01:55 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-06-11 18:20:54 +0100 |
| commit | cf7578995398e20d3ab0748e6d5f83ea6c7a0035 (patch) | |
| tree | 4b0c2a17f960d300f9475662e8e7e4c762fb1de0 /arch/mips/mips-boards/generic | |
| parent | 6a05888d713dd915d3268000a479e38646aa423f (diff) | |
[MIPS] SMTC: Fix build error caused by nonsense code.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/generic')
| -rw-r--r-- | arch/mips/mips-boards/generic/time.c | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 37735bfc3afd..b41db9e7ab1f 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -88,8 +88,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) * the general MIPS timer_interrupt routine. */ - int vpflags; - /* * We could be here due to timer interrupt, * perf counter overflow, or both. @@ -98,15 +96,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) perf_irq(); if (read_c0_cause() & (1 << 30)) { - /* If timer interrupt, make it de-assert */ - write_c0_compare (read_c0_count() - 1); - /* - * DVPE is necessary so long as cross-VPE interrupts - * are done via read-modify-write of Cause register. - */ - vpflags = dvpe(); - clear_c0_cause(CPUCTR_IMASKBIT); - evpe(vpflags); /* * There are things we only want to do once per tick * in an "MP" system. One TC of each VPE will take @@ -115,14 +104,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) * the tick on VPE 0 to run the full timer_interrupt(). */ if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL); - smtc_timer_broadcast(cpu_data[cpu].vpe_id); + timer_interrupt(irq, NULL); } else { write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); local_timer_interrupt(irq, dev_id); - smtc_timer_broadcast(cpu_data[cpu].vpe_id); } + smtc_timer_broadcast(cpu_data[cpu].vpe_id); } #else /* CONFIG_MIPS_MT_SMTC */ int r2 = cpu_has_mips_r2; |