Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:

 o Add basic support for the Mediatek/Ralink Wireless SoC family.

 o The Qualcomm Atheros platform is extended by support for the new
   QCA955X SoC series as well as a bunch of patches that get the code
   ready for OF support.

 o Lantiq and BCM47XX platform have a few improvements and bug fixes.

 o MIPS has sent a few patches that get the kernel ready for the
   upcoming microMIPS support.

 o The rest of the series is made up of small bug fixes and cleanups
   that relate to various parts of the MIPS code.  The biggy in there is
   a whitespace cleanup.  After I was sent another set of whitespace
   cleanup patches I decided it was the time to clean the whitespace
   "issues" for once and and that touches many files below arch/mips/.

Fix up silly conflicts, mostly due to whitespace cleanups.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
  MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
  MIPS: remove broken conditional inside vpe loader code
  MIPS: SMTC: fix implicit declaration of set_vi_handler
  MIPS: early_printk: drop __init annotations
  MIPS: Probe for and report hardware virtualization support.
  MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
  MIPS: ath79: add USB controller registration code for the QCA955X SoCs
  MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
  MIPS: ath79: add WMAC registration code for the QCA955X SoCs
  MIPS: ath79: register UART for the QCA955X SoCs
  MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
  MIPS: ath79: add GPIO setup code for the QCA955X SoCs
  MIPS: ath79: add IRQ handling code for the QCA955X SoCs
  MIPS: ath79: add clock setup code for the QCA955X SoCs
  MIPS: ath79: add SoC detection code for the QCA955X SoCs
  MIPS: ath79: add early printk support for the QCA955X SoCs
  MIPS: ath79: fix WMAC IRQ resource assignment
  mips: reserve elfcorehdr
  mips: Make sure kernel memory is in iomem
  MIPS: ath79: use dynamically allocated USB platform devices
  ...

13 files changed, 122 insertions, 199 deletions

diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index 626afeac4386..10ec701ce6c7 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -5,10 +5,12 @@
 # Copyright (C) 2008 Wind River Systems, Inc.
 #   written by Ralf Baechle <ralf@linux-mips.org>
 #
+# Copyright (C) 2012 MIPS Technoligies, Inc.  All rights reserved.
+# Steven J. Hill <sjhill@mips.com>
+#
 obj-y				:= sead3-lcd.o sead3-cmdline.o \
 				   sead3-display.o sead3-init.o sead3-int.o \
-				   sead3-mtd.o sead3-net.o \
-				   sead3-memory.o sead3-platform.o \
+				   sead3-mtd.o sead3-net.o sead3-platform.o \
 				   sead3-reset.o sead3-setup.o sead3-time.o
 
 obj-y				+= sead3-i2c-dev.o sead3-i2c.o \
@@ -17,3 +19,7 @@ obj-y				+= sead3-i2c-dev.o sead3-i2c.o \
 
 obj-$(CONFIG_EARLY_PRINTK)	+= sead3-console.o
 obj-$(CONFIG_USB_EHCI_HCD)	+= sead3-ehci.o
+obj-$(CONFIG_OF)		+= sead3.dtb.o
+
+$(obj)/%.dtb: $(obj)/%.dts
+	$(call if_changed,dtc)
diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c
index a95ac5985206..322148c353ed 100644
--- a/arch/mips/mti-sead3/leds-sead3.c
+++ b/arch/mips/mti-sead3/leds-sead3.c
@@ -33,12 +33,12 @@ static void sead3_fled_set(struct led_classdev *led_cdev,
 
 static struct led_classdev sead3_pled = {
 	.name		= "sead3::pled",
-	.brightness_set	= sead3_pled_set,
+	.brightness_set = sead3_pled_set,
 };
 
 static struct led_classdev sead3_fled = {
 	.name		= "sead3::fled",
-	.brightness_set	= sead3_fled_set,
+	.brightness_set = sead3_fled_set,
 };
 
 #ifdef CONFIG_PM
@@ -125,4 +125,3 @@ module_exit(sead3_led_exit);
 MODULE_AUTHOR("Kristian Kielhofner <kris@krisk.org>");
 MODULE_DESCRIPTION("SEAD3 LED driver");
 MODULE_LICENSE("GPL");
-
diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c
index b36739108a0f..2ddef19a9adc 100644
--- a/arch/mips/mti-sead3/sead3-console.c
+++ b/arch/mips/mti-sead3/sead3-console.c
@@ -10,8 +10,8 @@
 #include <linux/serial_reg.h>
 #include <linux/io.h>
 
-#define SEAD_UART1_REGS_BASE    0xbf000800   /* ttyS1 = DB9 port */
-#define SEAD_UART0_REGS_BASE    0xbf000900   /* ttyS0 = USB port   */
+#define SEAD_UART1_REGS_BASE	0xbf000800   /* ttyS1 = DB9 port */
+#define SEAD_UART0_REGS_BASE	0xbf000900   /* ttyS0 = USB port   */
 #define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4))
 
 static char console_port = 1;
diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c
index 8308c7fc188a..e389326cfa42 100644
--- a/arch/mips/mti-sead3/sead3-display.c
+++ b/arch/mips/mti-sead3/sead3-display.c
@@ -21,7 +21,7 @@ static unsigned int max_display_count;
 #define LCD_SETDDRAM			0x80
 #define LCD_IR_BF			0x80
 
-const char display_string[] = "               LINUX ON SEAD3               ";
+const char display_string[] = "		      LINUX ON SEAD3		   ";
 
 static void scroll_display_message(unsigned long data);
 static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0);
diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c
index 7aa2225e75b9..1f787a6a7878 100644
--- a/arch/mips/mti-sead3/sead3-i2c-drv.c
+++ b/arch/mips/mti-sead3/sead3-i2c-drv.c
@@ -13,32 +13,32 @@
 #include <linux/platform_device.h>
 
 #define PIC32_I2CxCON		0x0000
-#define  PIC32_I2CCON_ON	(1<<15)
-#define  PIC32_I2CCON_ACKDT	(1<<5)
-#define  PIC32_I2CCON_ACKEN	(1<<4)
-#define  PIC32_I2CCON_RCEN	(1<<3)
-#define  PIC32_I2CCON_PEN	(1<<2)
-#define  PIC32_I2CCON_RSEN	(1<<1)
-#define  PIC32_I2CCON_SEN	(1<<0)
+#define	 PIC32_I2CCON_ON	(1<<15)
+#define	 PIC32_I2CCON_ACKDT	(1<<5)
+#define	 PIC32_I2CCON_ACKEN	(1<<4)
+#define	 PIC32_I2CCON_RCEN	(1<<3)
+#define	 PIC32_I2CCON_PEN	(1<<2)
+#define	 PIC32_I2CCON_RSEN	(1<<1)
+#define	 PIC32_I2CCON_SEN	(1<<0)
 #define PIC32_I2CxCONCLR	0x0004
 #define PIC32_I2CxCONSET	0x0008
 #define PIC32_I2CxSTAT		0x0010
 #define PIC32_I2CxSTATCLR	0x0014
-#define  PIC32_I2CSTAT_ACKSTAT	(1<<15)
-#define  PIC32_I2CSTAT_TRSTAT	(1<<14)
-#define  PIC32_I2CSTAT_BCL	(1<<10)
-#define  PIC32_I2CSTAT_IWCOL	(1<<7)
-#define  PIC32_I2CSTAT_I2COV	(1<<6)
+#define	 PIC32_I2CSTAT_ACKSTAT	(1<<15)
+#define	 PIC32_I2CSTAT_TRSTAT	(1<<14)
+#define	 PIC32_I2CSTAT_BCL	(1<<10)
+#define	 PIC32_I2CSTAT_IWCOL	(1<<7)
+#define	 PIC32_I2CSTAT_I2COV	(1<<6)
 #define PIC32_I2CxBRG		0x0040
 #define PIC32_I2CxTRN		0x0050
 #define PIC32_I2CxRCV		0x0060
 
 static DEFINE_SPINLOCK(pic32_bus_lock);
 
-static void __iomem *bus_xfer   = (void __iomem *)0xbf000600;
+static void __iomem *bus_xfer	= (void __iomem *)0xbf000600;
 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 
-#define DELAY()	udelay(100)
+#define DELAY() udelay(100)
 
 static inline unsigned int ioready(void)
 {
diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c
index a958cad6fff6..f95abaa1aa5d 100644
--- a/arch/mips/mti-sead3/sead3-init.c
+++ b/arch/mips/mti-sead3/sead3-init.c
@@ -77,7 +77,6 @@ void __init prom_init(void)
 	board_ejtag_handler_setup = mips_ejtag_setup;
 
 	prom_init_cmdline();
-	prom_meminit();
 #ifdef CONFIG_EARLY_PRINTK
 	if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL)
 		prom_init_early_console(0);
@@ -89,3 +88,7 @@ void __init prom_init(void)
 		strcat(prom_getcmdline(), " console=ttyS0,38400n8r");
 #endif
 }
+
+void prom_free_prom_memory(void)
+{
+}
diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c
deleted file mode 100644
index da9244106f86..000000000000
--- a/arch/mips/mti-sead3/sead3-memory.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
- */
-#include <linux/bootmem.h>
-
-#include <asm/bootinfo.h>
-#include <asm/sections.h>
-#include <asm/mips-boards/prom.h>
-
-enum yamon_memtypes {
-	yamon_dontuse,
-	yamon_prom,
-	yamon_free,
-};
-
-static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
-
-/* determined physical memory size, not overridden by command line args  */
-unsigned long physical_memsize = 0L;
-
-struct prom_pmemblock * __init prom_getmdesc(void)
-{
-	char *memsize_str, *ptr;
-	unsigned int memsize;
-	static char cmdline[COMMAND_LINE_SIZE] __initdata;
-	long val;
-	int tmp;
-
-	/* otherwise look in the environment */
-	memsize_str = prom_getenv("memsize");
-	if (!memsize_str) {
-		pr_warn("memsize not set in boot prom, set to default 32Mb\n");
-		physical_memsize = 0x02000000;
-	} else {
-		tmp = kstrtol(memsize_str, 0, &val);
-		physical_memsize = (unsigned long)val;
-	}
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
-	/* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
-	   word of physical memory */
-	physical_memsize -= PAGE_SIZE;
-#endif
-
-	/* Check the command line for a memsize directive that overrides
-	   the physical/default amount */
-	strcpy(cmdline, arcs_cmdline);
-	ptr = strstr(cmdline, "memsize=");
-	if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
-		ptr = strstr(ptr, " memsize=");
-
-	if (ptr)
-		memsize = memparse(ptr + 8, &ptr);
-	else
-		memsize = physical_memsize;
-
-	memset(mdesc, 0, sizeof(mdesc));
-
-	mdesc[0].type = yamon_dontuse;
-	mdesc[0].base = 0x00000000;
-	mdesc[0].size = 0x00001000;
-
-	mdesc[1].type = yamon_prom;
-	mdesc[1].base = 0x00001000;
-	mdesc[1].size = 0x000ef000;
-
-	/*
-	 * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
-	 * south bridge and PCI access always forwarded to the ISA Bus and
-	 * BIOSCS# is always generated.
-	 * This mean that this area can't be used as DMA memory for PCI
-	 * devices.
-	 */
-	mdesc[2].type = yamon_dontuse;
-	mdesc[2].base = 0x000f0000;
-	mdesc[2].size = 0x00010000;
-
-	mdesc[3].type = yamon_dontuse;
-	mdesc[3].base = 0x00100000;
-	mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) -
-		mdesc[3].base;
-
-	mdesc[4].type = yamon_free;
-	mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
-	mdesc[4].size = memsize - mdesc[4].base;
-
-	return &mdesc[0];
-}
-
-static int __init prom_memtype_classify(unsigned int type)
-{
-	switch (type) {
-	case yamon_free:
-		return BOOT_MEM_RAM;
-	case yamon_prom:
-		return BOOT_MEM_ROM_DATA;
-	default:
-		return BOOT_MEM_RESERVED;
-	}
-}
-
-void __init prom_meminit(void)
-{
-	struct prom_pmemblock *p;
-
-	p = prom_getmdesc();
-
-	while (p->size) {
-		long type;
-		unsigned long base, size;
-
-		type = prom_memtype_classify(p->type);
-		base = p->base;
-		size = p->size;
-
-		add_memory_region(base, size, type);
-		p++;
-	}
-}
-
-void __init prom_free_prom_memory(void)
-{
-	unsigned long addr;
-	int i;
-
-	for (i = 0; i < boot_mem_map.nr_map; i++) {
-		if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
-			continue;
-
-		addr = boot_mem_map.map[i].addr;
-		free_init_pages("prom memory",
-				addr, addr + boot_mem_map.map[i].size);
-	}
-}
diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c
index 04d704df6098..dd11e7eb771c 100644
--- a/arch/mips/mti-sead3/sead3-net.c
+++ b/arch/mips/mti-sead3/sead3-net.c
@@ -19,8 +19,8 @@ static struct smsc911x_platform_config sead3_smsc911x_data = {
 
 struct resource sead3_net_resourcess[] = {
 	{
-		.start                  = 0x1f010000,
-		.end                    = 0x1f01ffff,
+		.start			= 0x1f010000,
+		.end			= 0x1f01ffff,
 		.flags			= IORESOURCE_MEM
 	},
 	{
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
index 9f0d89bc800e..eb2bf936d102 100644
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ b/arch/mips/mti-sead3/sead3-pic32-bus.c
@@ -17,16 +17,16 @@
 #define PIC32_SYSRD	0x02
 #define PIC32_WR	0x10
 #define PIC32_SYSWR	0x20
-#define PIC32_IRQ_CLR   0x40
+#define PIC32_IRQ_CLR	0x40
 #define PIC32_STATUS	0x80
 
-#define DELAY()	udelay(100)	/* FIXME: needed? */
+#define DELAY() udelay(100)	/* FIXME: needed? */
 
 /* spinlock to ensure atomic access to PIC32 */
 static DEFINE_SPINLOCK(pic32_bus_lock);
 
 /* FIXME: io_remap these */
-static void __iomem *bus_xfer   = (void __iomem *)0xbf000600;
+static void __iomem *bus_xfer	= (void __iomem *)0xbf000600;
 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 
 static inline unsigned int ioready(void)
diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
index 514675ed0cde..b921e5ec507c 100644
--- a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
+++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
@@ -19,40 +19,40 @@
 #define PIC32_I2CxCONCLR	0x0004
 #define PIC32_I2CxCONSET	0x0008
 #define PIC32_I2CxCONINV	0x000C
-#define  I2CCON_ON		(1<<15)
-#define  I2CCON_FRZ		(1<<14)
-#define  I2CCON_SIDL		(1<<13)
-#define  I2CCON_SCLREL		(1<<12)
-#define  I2CCON_STRICT		(1<<11)
-#define  I2CCON_A10M		(1<<10)
-#define  I2CCON_DISSLW		(1<<9)
-#define  I2CCON_SMEN		(1<<8)
-#define  I2CCON_GCEN		(1<<7)
-#define  I2CCON_STREN		(1<<6)
-#define  I2CCON_ACKDT		(1<<5)
-#define  I2CCON_ACKEN		(1<<4)
-#define  I2CCON_RCEN		(1<<3)
-#define  I2CCON_PEN		(1<<2)
-#define  I2CCON_RSEN		(1<<1)
-#define  I2CCON_SEN		(1<<0)
+#define	 I2CCON_ON		(1<<15)
+#define	 I2CCON_FRZ		(1<<14)
+#define	 I2CCON_SIDL		(1<<13)
+#define	 I2CCON_SCLREL		(1<<12)
+#define	 I2CCON_STRICT		(1<<11)
+#define	 I2CCON_A10M		(1<<10)
+#define	 I2CCON_DISSLW		(1<<9)
+#define	 I2CCON_SMEN		(1<<8)
+#define	 I2CCON_GCEN		(1<<7)
+#define	 I2CCON_STREN		(1<<6)
+#define	 I2CCON_ACKDT		(1<<5)
+#define	 I2CCON_ACKEN		(1<<4)
+#define	 I2CCON_RCEN		(1<<3)
+#define	 I2CCON_PEN		(1<<2)
+#define	 I2CCON_RSEN		(1<<1)
+#define	 I2CCON_SEN		(1<<0)
 
 #define PIC32_I2CxSTAT		0x0010
 #define PIC32_I2CxSTATCLR	0x0014
 #define PIC32_I2CxSTATSET	0x0018
 #define PIC32_I2CxSTATINV	0x001C
-#define  I2CSTAT_ACKSTAT	(1<<15)
-#define  I2CSTAT_TRSTAT		(1<<14)
-#define  I2CSTAT_BCL		(1<<10)
-#define  I2CSTAT_GCSTAT		(1<<9)
-#define  I2CSTAT_ADD10		(1<<8)
-#define  I2CSTAT_IWCOL		(1<<7)
-#define  I2CSTAT_I2COV		(1<<6)
-#define  I2CSTAT_DA		(1<<5)
-#define  I2CSTAT_P		(1<<4)
-#define  I2CSTAT_S		(1<<3)
-#define  I2CSTAT_RW		(1<<2)
-#define  I2CSTAT_RBF		(1<<1)
-#define  I2CSTAT_TBF		(1<<0)
+#define	 I2CSTAT_ACKSTAT	(1<<15)
+#define	 I2CSTAT_TRSTAT		(1<<14)
+#define	 I2CSTAT_BCL		(1<<10)
+#define	 I2CSTAT_GCSTAT		(1<<9)
+#define	 I2CSTAT_ADD10		(1<<8)
+#define	 I2CSTAT_IWCOL		(1<<7)
+#define	 I2CSTAT_I2COV		(1<<6)
+#define	 I2CSTAT_DA		(1<<5)
+#define	 I2CSTAT_P		(1<<4)
+#define	 I2CSTAT_S		(1<<3)
+#define	 I2CSTAT_RW		(1<<2)
+#define	 I2CSTAT_RBF		(1<<1)
+#define	 I2CSTAT_TBF		(1<<0)
 
 #define PIC32_I2CxADD		0x0020
 #define PIC32_I2CxADDCLR	0x0024
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
index 8ad46ad31b49..f012fd164cee 100644
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ b/arch/mips/mti-sead3/sead3-setup.c
@@ -6,6 +6,12 @@
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  */
 #include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+#include <linux/bootmem.h>
+
+#include <asm/mips-boards/generic.h>
+#include <asm/prom.h>
 
 int coherentio;		/* 0 => no DMA cache coherency (may be set by user) */
 int hw_coherentio;	/* 0 => no HW DMA cache coherency (reflects real HW) */
@@ -17,4 +23,25 @@ const char *get_system_type(void)
 
 void __init plat_mem_setup(void)
 {
+	/*
+	 * Load the builtin devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(&__dtb_start);
+}
+
+void __init device_tree_init(void)
+{
+	unsigned long base, size;
+
+	if (!initial_boot_params)
+		return;
+
+	base = virt_to_phys((void *)initial_boot_params);
+	size = be32_to_cpu(initial_boot_params->totalsize);
+
+	/* Before we do anything, lets reserve the dt blob */
+	reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+
+	unflatten_device_tree();
 }
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index 048e781a17a0..239e4e32757f 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -43,11 +43,11 @@ static unsigned int __init estimate_cpu_frequency(void)
 
 	local_irq_save(flags);
 
-	orig = readl(status_reg) & 0x2;               /* get original sample */
+	orig = readl(status_reg) & 0x2;		      /* get original sample */
 	/* wait for transition */
 	while ((readl(status_reg) & 0x2) == orig)
 		;
-	orig = orig ^ 0x2;                            /* flip the bit */
+	orig = orig ^ 0x2;			      /* flip the bit */
 
 	write_c0_count(0);
 
@@ -56,7 +56,7 @@ static unsigned int __init estimate_cpu_frequency(void)
 		/* wait for transition */
 		while ((readl(status_reg) & 0x2) == orig)
 			;
-		orig = orig ^ 0x2;                            /* flip the bit */
+		orig = orig ^ 0x2;			      /* flip the bit */
 		tick++;
 	}
 
@@ -71,7 +71,7 @@ static unsigned int __init estimate_cpu_frequency(void)
 		(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 		freq *= 2;
 
-	freq += 5000;        /* rounding */
+	freq += 5000;	     /* rounding */
 	freq -= freq%10000;
 
 	return freq ;
diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts
new file mode 100644
index 000000000000..658f43787056
--- /dev/null
+++ b/arch/mips/mti-sead3/sead3.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000;	// reserved
+/memreserve/ 0x00001000 0x000ef000;	// ROM data
+/memreserve/ 0x000f0000 0x004cc000;	// reserved
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mti,sead-3";
+
+	cpus {
+		cpu@0 {
+			compatible = "mti,mips14KEc", "mti,mips14Kc";
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};