diff options
| author | James Hogan <james.hogan@imgtec.com> | 2016-04-28 17:06:16 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-09 12:00:05 +0200 |
| commit | 32eb6e8bee147b45e5e59230630d59541ccbb6e5 (patch) | |
| tree | 5da83f0a03e9bc7f0c6c0db006cf469f09199717 /arch/mips/netlogic/common/smpboot.S | |
| parent | 128639395b2ceacc6a56a0141d0261012bfe04d3 (diff) | |
MIPS: Netlogic: Fix CP0_EBASE redefinition warnings
A couple of netlogic assembly files define CP0_EBASE to $15, the same as
CP0_PRID in mipsregs.h, and use it for accessing both CP0_PRId and
CP0_EBase registers. However commit 609cf6f2291a ("MIPS: CPS: Early
debug using an ns16550-compatible UART") added a different definition of
CP0_EBASE to mipsregs.h, which included a register select of 1. This
causes harmless build warnings like the following:
arch/mips/netlogic/common/reset.S:53:0: warning: "CP0_EBASE" redefined
#define CP0_EBASE $15
^
In file included from arch/mips/netlogic/common/reset.S:41:0:
./arch/mips/include/asm/mipsregs.h:63:0: note: this is the location of the previous definition
#define CP0_EBASE $15, 1
^
Update the code to use the definitions from mipsregs.h for accessing
both registers.
Fixes: 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13183/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic/common/smpboot.S')
| -rw-r--r-- | arch/mips/netlogic/common/smpboot.S | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 805355b0bd05..f0cc4c9de2bb 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -48,8 +48,6 @@ #include <asm/netlogic/xlp-hal/sys.h> #include <asm/netlogic/xlp-hal/cpucontrol.h> -#define CP0_EBASE $15 - .set noreorder .set noat .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ @@ -86,7 +84,7 @@ NESTED(nlm_boot_secondary_cpus, 16, sp) PTR_L gp, 0(t1) /* a0 has the processor id */ - mfc0 a0, CP0_EBASE, 1 + mfc0 a0, CP0_EBASE andi a0, 0x3ff /* a0 <- node/core */ PTR_LA t0, nlm_early_init_secondary jalr t0 |