diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-04-13 18:10:14 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2012-04-16 09:52:52 +0800 |
| commit | 027d11038da5e8c0585c1b685282d7b0e0c93c6a (patch) | |
| tree | 4357b6cc3aa604fb76bb68808a1f9991fc33ac01 /arch/mips/nxp/pnx8550/common | |
| parent | 7b3296b71d51ba7efe82aad13cf908baf2c4963c (diff) | |
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'arch/mips/nxp/pnx8550/common')
0 files changed, 0 insertions, 0 deletions