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authorIngo Molnar <mingo@elte.hu>2008-06-16 11:15:58 +0200
committerIngo Molnar <mingo@elte.hu>2008-06-16 11:15:58 +0200
commite765ee90da62535ac7d7a97f2464f9646539d683 (patch)
tree7a9cecce5aab958938e9a3bf46c2302d6af1958c /arch/mips/pci/ops-bridge.c
parenta4500b84c51645bbc86be3ca84f2252b7ada060f (diff)
parent066519068ad2fbe98c7f45552b1f592903a9c8c8 (diff)
Diffstat (limited to 'arch/mips/pci/ops-bridge.c')
-rw-r--r--arch/mips/pci/ops-bridge.c20
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 1fa09929cd7a..b46b3e211775 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -14,6 +14,22 @@
#include <asm/sn/sn0/hub.h>
/*
+ * Most of the IOC3 PCI config register aren't present
+ * we emulate what is needed for a normal PCI enumeration
+ */
+static u32 emulate_ioc3_cfg(int where, int size)
+{
+ if (size == 1 && where == 0x3d)
+ return 0x01;
+ else if (size == 2 && where == 0x3c)
+ return 0x0100;
+ else if (size == 4 && where == 0x3c)
+ return 0x00000100;
+
+ return 0;
+}
+
+/*
* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
* not really documented, so right now I can't write code which uses it.
* Therefore we use type 0 accesses for now even though they won't work
@@ -64,7 +80,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}
@@ -127,7 +143,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}