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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-07-02 21:06:03 +0200
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 18:44:31 +0100
commit8736595bb2b0ce6188ca31308c40921f3f02f35b (patch)
tree823a1f7fb6e9f2477607886fb1d3eb42523a7a37 /arch/mips/pci
parentf2bc713f15103372c0efab5fc09dd813655c5096 (diff)
[MIPS] Enable FAST-20 for onboard scsi
Both onboard controller of the O2 support FAST-20 transfer speeds, but the bit, which signals that to the aic driver, isn't set. Instead of adding detection code to the scsi driver, we just fake the missing bit in the PCI config space of the scsi chips. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/ops-mace.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index e95881897ec9..1cfb5588699f 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -61,6 +61,13 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
/* ack possible master abort */
mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
mace->pci.control = control;
+ /*
+ * someone forgot to set the ultra bit for the onboard
+ * scsi chips; we fake it here
+ */
+ if (bus->number == 0 && reg == 0x40 && size == 4 &&
+ (devfn == (1 << 3) || devfn == (2 << 3)))
+ *val |= 0x1000;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);