Merge branch 'linus' into x86/threadinfotip-x86-threadinfo-2008-06-23_09.53_Mon

6 files changed, 100 insertions, 72 deletions

diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
index 00c36c9dbe0e..e2ddfc49237c 100644
--- a/arch/mips/pci/fixup-au1000.c
+++ b/arch/mips/pci/fixup-au1000.c
@@ -1,10 +1,9 @@
 /*
  * BRIEF MODULE DESCRIPTION
- *	Board specific pci fixups.
+ *	Board specific PCI fixups.
  *
- * Copyright 2001-2003 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *         	ppopov@mvista.com or source@mvista.com
+ * Copyright 2001-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 1314bd58f036..9a57c5ab91dd 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -1,10 +1,9 @@
 /*
  * BRIEF MODULE DESCRIPTION
- *	Alchemy/AMD Au1x00 PCI support.
+ *	Alchemy/AMD Au1xx0 PCI support.
  *
- * Copyright 2001-2003, 2007 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *         	ppopov@mvista.com or source@mvista.com
+ * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  Support for all devices (greater than 16) added by David Gathright.
  *
@@ -28,6 +27,7 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
+
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
@@ -36,9 +36,9 @@
 
 #include <asm/mach-au1x00/au1000.h>
 
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
+#undef	DEBUG
+#ifdef	DEBUG
+#define DBG(x...) printk(KERN_DEBUG x)
 #else
 #define DBG(x...)
 #endif
@@ -46,7 +46,6 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-
 int (*board_pci_idsel)(unsigned int devsel, int assert);
 
 void mod_wired_entry(int entry, unsigned long entrylo0,
@@ -92,10 +91,9 @@ void __init au1x_pci_cfg_init(void)
 }
 
 static int config_access(unsigned char access_type, struct pci_bus *bus,
-			 unsigned int dev_fn, unsigned char where,
-			 u32 * data)
+			 unsigned int dev_fn, unsigned char where, u32 *data)
 {
-#if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 	unsigned int device = PCI_SLOT(dev_fn);
 	unsigned int function = PCI_FUNC(dev_fn);
 	unsigned long offset, status;
@@ -114,38 +112,36 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
 			Au1500_PCI_STATCMD);
 	au_sync_udelay(1);
 
-	/* Allow board vendors to implement their own off-chip idsel.
+	/*
+	 * Allow board vendors to implement their own off-chip IDSEL.
 	 * If it doesn't succeed, may as well bail out at this point.
 	 */
-	if (board_pci_idsel) {
-		if (board_pci_idsel(device, 1) == 0) {
-			*data = 0xffffffff;
-			local_irq_restore(flags);
-			return -1;
-		}
+	if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
+		*data = 0xffffffff;
+		local_irq_restore(flags);
+		return -1;
 	}
 
-        /* setup the config window */
-        if (bus->number == 0) {
-                cfg_base = ((1<<device)<<11);
-        } else {
-                cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
-        }
+	/* Setup the config window */
+	if (bus->number == 0)
+		cfg_base = (1 << device) << 11;
+	else
+		cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
 
-        /* setup the lower bits of the 36 bit address */
-        offset = (function << 8) | (where & ~0x3);
-	/* pick up any address that falls below the page mask */
+	/* Setup the lower bits of the 36-bit address */
+	offset = (function << 8) | (where & ~0x3);
+	/* Pick up any address that falls below the page mask */
 	offset |= cfg_base & ~PAGE_MASK;
 
-	/* page boundary */
+	/* Page boundary */
 	cfg_base = cfg_base & PAGE_MASK;
 
 	/*
 	 * To improve performance, if the current device is the same as
 	 * the last device accessed, we don't touch the TLB.
 	 */
-	entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
-	entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
+	entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
+	entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
 	if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
 		mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
 				(unsigned long)pci_cfg_vm->addr, PM_4K);
@@ -153,38 +149,37 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
 		last_entryLo1 = entryLo1;
 	}
 
-	if (access_type == PCI_ACCESS_WRITE) {
+	if (access_type == PCI_ACCESS_WRITE)
 		au_writel(*data, (int)(pci_cfg_vm->addr + offset));
-	} else {
+	else
 		*data = au_readl((int)(pci_cfg_vm->addr + offset));
-	}
+
 	au_sync_udelay(2);
 
-	DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
-			access_type, bus->number, device, where, *data, offset);
+	DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
+	    access_type, bus->number, device, where, *data, offset);
 
-	/* check master abort */
+	/* Check master abort */
 	status = au_readl(Au1500_PCI_STATCMD);
 
-	if (status & (1<<29)) {
+	if (status & (1 << 29)) {
 		*data = 0xffffffff;
 		error = -1;
 		DBG("Au1x Master Abort\n");
 	} else if ((status >> 28) & 0xf) {
-		DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));
+		DBG("PCI ERR detected: device %u, status %lx\n",
+		    device, (status >> 28) & 0xf);
 
-		/* clear errors */
+		/* Clear errors */
 		au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
 
 		*data = 0xffffffff;
 		error = -1;
 	}
 
-	/* Take away the idsel.
-	*/
-	if (board_pci_idsel) {
+	/* Take away the IDSEL. */
+	if (board_pci_idsel)
 		(void)board_pci_idsel(device, 0);
-	}
 
 	local_irq_restore(flags);
 	return error;
@@ -192,7 +187,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
 }
 
 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
-			    int where, u8 * val)
+			    int where,	u8 *val)
 {
 	u32 data;
 	int ret;
@@ -206,9 +201,8 @@ static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 	return ret;
 }
 
-
 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
-			    int where, u16 * val)
+			    int where, u16 *val)
 {
 	u32 data;
 	int ret;
@@ -221,7 +215,7 @@ static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 }
 
 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
-			     int where, u32 * val)
+			     int where, u32 *val)
 {
 	int ret;
 
@@ -229,9 +223,8 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 	return ret;
 }
 
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
-		  u8 val)
+static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
+			     int where, u8 val)
 {
 	u32 data = 0;
 
@@ -239,7 +232,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 		return -1;
 
 	data = (data & ~(0xff << ((where & 3) << 3))) |
-	    (val << ((where & 3) << 3));
+	       (val << ((where & 3) << 3));
 
 	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 		return -1;
@@ -247,9 +240,8 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
-		  u16 val)
+static int write_config_word(struct pci_bus *bus, unsigned int devfn,
+			     int where, u16 val)
 {
 	u32 data = 0;
 
@@ -257,18 +249,16 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 		return -1;
 
 	data = (data & ~(0xffff << ((where & 3) << 3))) |
-	    (val << ((where & 3) << 3));
+	       (val << ((where & 3) << 3));
 
 	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 		return -1;
 
-
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
-		   u32 val)
+static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
+			      int where, u32 val)
 {
 	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 		return -1;
@@ -277,18 +267,20 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 }
 
 static int config_read(struct pci_bus *bus, unsigned int devfn,
-		       int where, int size, u32 * val)
+		       int where, int size, u32 *val)
 {
 	switch (size) {
 	case 1: {
 			u8 _val;
 			int rc = read_config_byte(bus, devfn, where, &_val);
+
 			*val = _val;
 			return rc;
 		}
-       case 2: {
+	case 2: {
 			u16 _val;
 			int rc = read_config_word(bus, devfn, where, &_val);
+
 			*val = _val;
 			return rc;
 		}
@@ -310,7 +302,6 @@ static int config_write(struct pci_bus *bus, unsigned int devfn,
 	}
 }
 
-
 struct pci_ops au1x_pci_ops = {
 	config_read,
 	config_write
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 1fa09929cd7a..b46b3e211775 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -14,6 +14,22 @@
 #include <asm/sn/sn0/hub.h>
 
 /*
+ * Most of the IOC3 PCI config register aren't present
+ * we emulate what is needed for a normal PCI enumeration
+ */
+static u32 emulate_ioc3_cfg(int where, int size)
+{
+	if (size == 1 && where == 0x3d)
+		return 0x01;
+	else if (size == 2 && where == 0x3c)
+		return 0x0100;
+	else if (size == 4 && where == 0x3c)
+		return 0x00000100;
+
+	return 0;
+}
+
+/*
  * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
  * not really documented, so right now I can't write code which uses it.
  * Therefore we use type 0 accesses for now even though they won't work
@@ -64,7 +80,7 @@ oh_my_gawd:
 	 * generic PCI code a chance to look at the wrong register.
 	 */
 	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
-		*value = 0;
+		*value = emulate_ioc3_cfg(where, size);
 		return PCIBIOS_SUCCESSFUL;
 	}
 
@@ -127,7 +143,7 @@ oh_my_gawd:
 	 * generic PCI code a chance to look at the wrong register.
 	 */
 	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
-		*value = 0;
+		*value = emulate_ioc3_cfg(where, size);
 		return PCIBIOS_SUCCESSFUL;
 	}
 
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index bb64828a92fe..a18516925cdd 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
 	static int num_bridges = 0;
 	bridge_t *bridge;
 	int slot;
+	extern int pci_probe_only;
+
+	pci_probe_only = 1;
 
 	printk("a bridge\n");
 
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
 	 */
 	bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
 	                         BRIDGE_CTRL_MEM_SWAP;
+#ifdef CONFIG_PAGE_SIZE_4KB
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#else /* 16kB or larger */
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#endif
 
 	/*
 	 * Hmm...  IRIX sets additional bits in the address which
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 42e4d2c800fa..2a09ad91ec8c 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -207,6 +207,7 @@ struct pci_controller sb1250_controller = {
 
 static int __init sb1250_pcibios_init(void)
 {
+	void __iomem *io_map_base;
 	uint32_t cmdreg;
 	uint64_t reg;
 	extern int pci_probe_only;
@@ -253,12 +254,13 @@ static int __init sb1250_pcibios_init(void)
 	 * works correctly with most of Linux's drivers.
 	 * XXX ehs: Should this happen in PCI Device mode?
 	 */
-
-	set_io_port_base((unsigned long)
-			 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
 	isa_slot_offset = (unsigned long)
 	    ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
 
+	io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
+	sb1250_controller.io_map_base = io_map_base;
+	set_io_port_base((unsigned long)io_map_base);
+
 #ifdef CONFIG_SIBYTE_HAS_LDT
 	/*
 	 * Also check the LDT bridge's enable, just in case we didn't
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 33c4f683d067..d1e049b55f34 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2001-2003 MontaVista Software Inc.
  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
- *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *  Copyright (C) 2004-2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
  *  Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -300,6 +300,18 @@ static int __init vr41xx_pciu_init(void)
 		ioport_resource.end = IO_PORT_RESOURCE_END;
 	}
 
+	if (setup->master_io) {
+		void __iomem *io_map_base;
+		struct resource *res = vr41xx_pci_controller.io_resource;
+		master = setup->master_io;
+		io_map_base = ioremap(master->bus_base_address,
+				      res->end - res->start + 1);
+		if (!io_map_base)
+			return -EBUSY;
+
+		vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
+	}
+
 	register_pci_controller(&vr41xx_pci_controller);
 
 	return 0;