diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-04-03 17:56:36 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-04-19 04:14:21 +0200 |
| commit | e4ac58afdfac792c0583af30dbd9eae53e24c78b (patch) | |
| tree | 7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/vr41xx/common/irq.c | |
| parent | d35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff) | |
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers
frequently do a better job than the cut and paste type of handlers many
boards had. And finally having all the stuff done in a single place
also means alot of bug potencial for the MT ASE is gone.
The only surviving handler in assembler is the DECstation one; I hope
Maciej will rewrite it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/vr41xx/common/irq.c')
| -rw-r--r-- | arch/mips/vr41xx/common/irq.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 61aa264275ff..86796bb63c3c 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -59,7 +59,7 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *) EXPORT_SYMBOL_GPL(cascade_irq); -asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) +static void irq_dispatch(unsigned int irq, struct pt_regs *regs) { irq_cascade_t *cascade; irq_desc_t *desc; @@ -84,11 +84,32 @@ asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) do_IRQ(irq, regs); } -extern asmlinkage void vr41xx_handle_interrupt(void); +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + do_IRQ(7, regs); + else if (pending & 0x7800) { + if (pending & CAUSEF_IP3) + irq_dispatch(3, regs); + else if (pending & CAUSEF_IP4) + irq_dispatch(4, regs); + else if (pending & CAUSEF_IP5) + irq_dispatch(5, regs); + else if (pending & CAUSEF_IP6) + irq_dispatch(6, regs); + } else if (pending & CAUSEF_IP2) + irq_dispatch(2, regs); + else if (pending & CAUSEF_IP0) + do_IRQ(0, regs); + else if (pending & CAUSEF_IP1) + do_IRQ(1, regs); + else + spurious_interrupt(regs); +} void __init arch_init_irq(void) { mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); - - set_except_vector(0, vr41xx_handle_interrupt); } |