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authorPaul Burton <paul.burton@imgtec.com>2014-03-21 15:20:31 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 18:17:12 +0200
commitfa12b773b7fb5830469086d36eb5be9f6b512f4d (patch)
tree7f1f4ce47d8b0a24c5b642c84fdb2f9e2cb7a43b /arch/mips
parent024e6a8b5bb16b1372eec744f417779aa4b59d1c (diff)
MIPS: Malta: Setup PM I/O region on boot
This patch ensures that the kernel sets a sane base address for the PIIX4 PM I/O register region during boot. Without this the kernel may not successfully claim the region as a resource if the bootloader didn't configure the region. With this patch the kernel will always succeed with: pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI The lack of the resource claiming is easily reproducible without this patch using current versions of QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Tested-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6641/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h5
-rw-r--r--arch/mips/pci/fixup-malta.c13
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 836e2ede24de..9cf54041d416 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -50,4 +50,9 @@
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
+/* Power Management Configuration Space */
+#define PIIX4_FUNC3_PMBA 0x40
+#define PIIX4_FUNC3_PMREGMISC 0x80
+#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0)
+
#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 7a0eda782e35..2f9e52a1a750 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -51,6 +51,19 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
return 0;
}
+static void malta_piix_func3_base_fixup(struct pci_dev *dev)
+{
+ /* Set a sane PM I/O base address */
+ pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
+
+ /* Enable access to the PM I/O region */
+ pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
+ PIIX4_FUNC3_PMREGMISC_EN);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
+ malta_piix_func3_base_fixup);
+
static void malta_piix_func0_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;