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authorTomi Valkeinen <tomi.valkeinen@ideasonboard.com>2023-06-16 12:02:42 +0300
committerFrancesco Dolcini <francesco.dolcini@toradex.com>2023-06-19 15:54:30 +0200
commit976881c4059ff675a9ed9447a06ae15d6b93f13b (patch)
tree06cbc388ebb720916c769b28078ba908f8e66884 /arch/mips
parent80b2ca52d8237aaddeb5725b3e51c030ac6512d1 (diff)
drm/bridge: tc358768: Attempt to fix DSI horizontal timings
The DSI horizontal timing calculations done by the driver seem to often lead to underflows or overflows, depending on the videomode. There are two main things the current driver doesn't seem to get right: DSI HSW and HFP, and VSDly. However, even following Toshiba's documentation it seems we don't always get a working display. This patch attems to fix the horizontal timings for DSI event mode, and on a system with a DSI->HDMI encoder, a lot of standard HDMI modes now seem to work. The work relies on Toshiba's documentation, but also quite a bit on empirical testing. Also add quite a bit timing related debug prints to make it easier to improve on this later. I am not able to test pulse mode, and this patch doesn't attempt to fix it. However, the VSDly calculation also affects pulse mode, so this might cause a regression. Upstream-Status: Pending Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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