diff options
| author | Akira Takeuchi <takeuchi.akr@jp.panasonic.com> | 2010-10-27 17:28:39 +0100 |
|---|---|---|
| committer | David Howells <dhowells@redhat.com> | 2010-10-27 17:28:39 +0100 |
| commit | 06019be31a1b5812eec5bb3e1dbdeced04950e8e (patch) | |
| tree | c885748da5ba7232877cb509ba59d5c0aa1bc43a /arch/mn10300 | |
| parent | a116956423e1cdc4398110bdc66d66ae4c5ba90f (diff) | |
MN10300: Don't hard code the cacheline size in register defs
Don't hard code the cacheline size in the cache control register definitions.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/mn10300')
| -rw-r--r-- | arch/mn10300/include/asm/cache.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h index 781bf613366d..f29cde2cfc91 100644 --- a/arch/mn10300/include/asm/cache.h +++ b/arch/mn10300/include/asm/cache.h @@ -43,14 +43,18 @@ /* instruction cache access registers */ #define ICACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) + __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) #define ICACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES, u32) -/* instruction cache access registers */ +/* data cache access registers */ #define DCACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) + __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) #define DCACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES, u32) #endif /* _ASM_CACHE_H */ |