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authorJames Bottomley <James.Bottomley@HansenPartnership.com>2010-12-22 10:22:11 -0600
committerJames Bottomley <James.Bottomley@suse.de>2011-01-15 08:44:40 -0600
commitf311847c2fcebd81912e2f0caf8a461dec28db41 (patch)
tree802ef2aa01bd0d662e60412366a40c827fd3e875 /arch/parisc/kernel/traps.c
parent38567333a6dabd0f2b4150e9fb6dd8e3ba2985e5 (diff)
parisc: flush pages through tmpalias space
The kernel has an 8M tmpailas space (originally designed for copying and clearing pages but now only used for clearing). The idea is to place zeros into the cache above a physical page rather than into the physical page and flush the cache, because often the zeros end up being replaced quickly anyway. We can also use the tmpalias space for flushing a page. The difference here is that we have to do tmpalias processing in the non access data and instruction traps. The principle is the same: as long as we know the physical address and have a virtual address congruent to the real one, the flush will be effective. In order to use the tmpalias space, the icache miss path has to be enhanced to check for the alias region to make the fic instruction effective. Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'arch/parisc/kernel/traps.c')
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