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| author | Heiko Carstens <heiko.carstens@de.ibm.com> | 2016-12-28 11:33:48 +0100 |
|---|---|---|
| committer | Sasha Levin <alexander.levin@verizon.com> | 2017-07-31 13:37:51 -0400 |
| commit | 29ebc142b0b9559c6ed1d9a2df1174032d6ff380 (patch) | |
| tree | 1ee4f04c7479d8bd0131f78f65d884c3707cd8f5 /arch/parisc | |
| parent | 318c1207565009f2bc94d5ff28383b5390079c12 (diff) | |
s390/ctl_reg: make __ctl_load a full memory barrier
[ Upstream commit e991c24d68b8c0ba297eeb7af80b1e398e98c33f ]
We have quite a lot of code that depends on the order of the
__ctl_load inline assemby and subsequent memory accesses, like
e.g. disabling lowcore protection and the writing to lowcore.
Since the __ctl_load macro does not have memory barrier semantics, nor
any other dependencies the compiler is, theoretically, free to shuffle
code around. Or in other words: storing to lowcore could happen before
lowcore protection is disabled.
In order to avoid this class of potential bugs simply add a full
memory barrier to the __ctl_load macro.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Diffstat (limited to 'arch/parisc')
0 files changed, 0 insertions, 0 deletions