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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2007-12-21 15:39:31 +1100
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-12-23 13:14:13 -0600
commitd23f5099297c0f017ba4fb165dc9879bda11f9ce (patch)
tree0a43ca1a2090643290f02115526875bdf6390a10 /arch/powerpc/boot/dcr.h
parent007b6aa8114550c59373c751ac9cc9f356a0a81f (diff)
[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library
This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
-rw-r--r--arch/powerpc/boot/dcr.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 83b88aa92888..8e7ee2a4298f 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -14,12 +14,20 @@
#define DCRN_SDRAM0_CFGADDR 0x010
#define DCRN_SDRAM0_CFGDATA 0x011
+#define SDRAM0_READ(offset) ({\
+ mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+ mfdcr(DCRN_SDRAM0_CFGDATA); })
+#define SDRAM0_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+ mtdcr(DCRN_SDRAM0_CFGDATA, data); })
+
#define SDRAM0_B0CR 0x40
#define SDRAM0_B1CR 0x44
#define SDRAM0_B2CR 0x48
#define SDRAM0_B3CR 0x4c
-static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
+static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
+ SDRAM0_B2CR, SDRAM0_B3CR };
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000