diff options
| author | Igal Liberman <Igal.Liberman@freescale.com> | 2015-08-03 11:14:10 +0300 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-03-11 20:01:38 -0600 |
| commit | 84e0f1c138061c2494d240f9ad3f94edcf69e29d (patch) | |
| tree | 550d83011010112e06c53764b5b3d16e53a1c852 /arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | |
| parent | 334479d1ccc2dd8f3b4a66a8aa8ff72ef93e4b67 (diff) | |
powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s)
Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming <afleming@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t104xrdb.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi index 830ea484295b..521a50b7ddd9 100644 --- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi +++ b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi @@ -1,7 +1,7 @@ /* * T1040RDB/T1042RDB Device Tree Source * - * Copyright 2014 Freescale Semiconductor Inc. + * Copyright 2014 - 2015 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,12 @@ */ / { + aliases { + phy_rgmii_0 = &phy_rgmii_0; + phy_rgmii_1 = &phy_rgmii_1; + phy_sgmii_2 = &phy_sgmii_2; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -125,6 +131,31 @@ }; }; + fman@400000 { + ethernet@e6000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio0: mdio@fc000 { + phy_sgmii_2: ethernet-phy@03 { + reg = <0x03>; + }; + + phy_rgmii_0: ethernet-phy@01 { + reg = <0x01>; + }; + + phy_rgmii_1: ethernet-phy@02 { + reg = <0x02>; + }; + }; + }; }; pci0: pcie@ffe240000 { |