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authorJia Hongtao <B38951@freescale.com>2012-07-12 17:36:16 +0800
committerKumar Gala <galak@kernel.crashing.org>2012-07-12 10:08:09 -0500
commitb915341b4be29b3b2c02da932b69871e9b55ca4b (patch)
tree0a2f1f5cb982058e1be68217b1d9e33ea58c0c6e /arch/powerpc/boot/dts/mpc8572ds.dtsi
parent9653018b615b36eb1c221bfd1db5d47e1466cfd8 (diff)
powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DS
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8572ds.dtsi')
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index 14178944e220..357490bb84da 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -169,6 +169,23 @@
reg = <0x3>;
};
+ sgmii_phy0: sgmii-phy@0 {
+ interrupts = <6 1 0 0>;
+ reg = <0x1c>;
+ };
+ sgmii_phy1: sgmii-phy@1 {
+ interrupts = <6 1 0 0>;
+ reg = <0x1d>;
+ };
+ sgmii_phy2: sgmii-phy@2 {
+ interrupts = <7 1 0 0>;
+ reg = <0x1e>;
+ };
+ sgmii_phy3: sgmii-phy@3 {
+ interrupts = <7 1 0 0>;
+ reg = <0x1f>;
+ };
+
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";