Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpctip-x86-urgent-2008-05-17-17-16-08tip-x86-setup-2008-05-30_12.10_Fritip-x86-mtrr-2008-05-16-12-09-30tip-x86-cleanups-2008-05-16-11-16-08tip-tip-2008-05-26_08_52_Montip-timers-hrtimers-2008-05-30_12.09_Fritip-timers-hpet-2008-05-30_12.09_Fritip-sched-2008-05-26_08_52_Montip-core-locking-2008-05-26_08_52_Mon

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  [POWERPC] macintosh: Replace deprecated __initcall with device_initcall
  [POWERPC] cell: Fix section mismatches in io-workarounds code
  [POWERPC] spufs: Fix compile error
  [POWERPC] Fix uninitialized variable bug in copy_{to|from}_user
  [POWERPC] Add null pointer check to of_find_property
  [POWERPC] vmemmap fixes to use smaller pages
  [POWERPC] spufs: Fix pointer reference in find_victim
  [POWERPC] 85xx: SBC8548 - Add flash support and HW Rev reporting
  [POWERPC] 85xx: Fix some sparse warnings for 85xx MDS
  [POWERPC] 83xx: Enable DMA engine on the MPC8377 MDS board.
  [POWERPC] 86xx: mpc8610_hpcd: fix second serial port
  [POWERPC] 86xx: mpc8610_hpcd: add support for NOR and NAND flashes
  [POWERPC] 85xx: Add 8568 PHY workarounds to board code
  [POWERPC] 86xx: mpc8610_hpcd: use ULI526X driver for on-board ethernet

3 files changed, 178 insertions, 3 deletions

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index eac8e1b59496..1e7802cc31ae 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -268,6 +268,33 @@
 			interrupt-parent = <&ipic>;
 		};
 
+		dma@82a8 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8349-dma";
+			reg = <0x82a8 4>;
+			ranges = <0 0x8100 0x1a8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <0x47 8>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8349-dma-channel";
+				reg = <0 0x80>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8349-dma-channel";
+				reg = <0x80 0x80>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8349-dma-channel";
+				reg = <0x100 0x80>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8349-dma-channel";
+				reg = <0x180 0x28>;
+			};
+		};
+
 		/* IPIC
 		 * interrupts cell = <intr #, sense>
 		 * sense values match linux IORESOURCE_IRQ_* defines:
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index bba234eb14a9..08a780d89807 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -46,9 +46,63 @@
 		reg = <0x00000000 0x20000000>;	// 512M at 0x0
 	};
 
-	board-control@e8000000 {
-		compatible = "fsl,fpga-pixis";
-		reg = <0xe8000000 32>;		// pixis at 0xe8000000
+	localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
+		reg = <0xe0005000 0x1000>;
+		interrupts = <19 2>;
+		interrupt-parent = <&mpic>;
+		ranges = <0 0 0xf8000000 0x08000000
+			  1 0 0xf0000000 0x08000000
+			  2 0 0xe8400000 0x00008000
+			  4 0 0xe8440000 0x00008000
+			  5 0 0xe8480000 0x00008000
+			  6 0 0xe84c0000 0x00008000
+			  3 0 0xe8000000 0x00000020>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		flash@1,0 {
+			compatible = "cfi-flash";
+			reg = <1 0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		flash@2,0 {
+			compatible = "fsl,mpc8610-fcm-nand",
+				     "fsl,elbc-fcm-nand";
+			reg = <2 0 0x8000>;
+		};
+
+		flash@4,0 {
+			compatible = "fsl,mpc8610-fcm-nand",
+				     "fsl,elbc-fcm-nand";
+			reg = <4 0 0x8000>;
+		};
+
+		flash@5,0 {
+			compatible = "fsl,mpc8610-fcm-nand",
+				     "fsl,elbc-fcm-nand";
+			reg = <5 0 0x8000>;
+		};
+
+		flash@6,0 {
+			compatible = "fsl,mpc8610-fcm-nand",
+				     "fsl,elbc-fcm-nand";
+			reg = <6 0 0x8000>;
+		};
+
+		board-control@3,0 {
+			compatible = "fsl,fpga-pixis";
+			reg = <3 0 0x20>;
+		};
 	};
 
 	soc@e0000000 {
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index b86e65d926c1..22d967178fe9 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -52,6 +52,99 @@
 		reg = <0x00000000 0x10000000>;
 	};
 
+	localbus@e0000000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		reg = <0xe0000000 0x5000>;
+		interrupt-parent = <&mpic>;
+
+		ranges = <0x0 0x0 0xff800000 0x00800000		/*8MB Flash*/
+			  0x3 0x0 0xf0000000 0x04000000		/*64MB SDRAM*/
+			  0x4 0x0 0xf4000000 0x04000000 	/*64MB SDRAM*/
+			  0x5 0x0 0xf8000000 0x00b10000		/* EPLD */
+			  0x6 0x0 0xfb800000 0x04000000>;	/*64MB Flash*/
+
+
+		flash@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x800000>;
+			bank-width = <1>;
+			device-width = <1>;
+			partition@0x0 {
+				label = "space";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition@0x100000 {
+				label = "bootloader";
+				reg = <0x00100000 0x00700000>;
+				read-only;
+			};
+		};
+
+		epld@5,0 {
+			compatible = "wrs,epld-localbus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			reg = <0x5 0x0 0x00b10000>;
+			ranges = <
+				0x0 0x0 0x5 0x000000 0x1fff	/* LED */
+				0x1 0x0 0x5 0x100000 0x1fff	/* Switches */
+				0x3 0x0 0x5 0x300000 0x1fff	/* HW Rev. */
+				0xb 0x0	0x5 0xb00000 0x1fff	/* EEPROM */
+			>;
+
+			led@0,0 {
+				compatible = "led";
+				reg = <0x0 0x0 0x1fff>;
+			};
+
+			switches@1,0 {
+				compatible = "switches";
+				reg = <0x1 0x0 0x1fff>;
+			};
+
+			hw-rev@3,0 {
+				compatible = "hw-rev";
+				reg = <0x3 0x0 0x1fff>;
+			};
+
+			eeprom@b,0 {
+				compatible = "eeprom";
+				reg = <0xb 0 0x1fff>;
+			};
+
+		};
+
+		alt-flash@6,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x6 0x0 0x04000000>;
+			compatible = "cfi-flash";
+			bank-width = <4>;
+			device-width = <1>;
+			partition@0x0 {
+				label = "bootloader";
+				reg = <0x00000000 0x00100000>;
+				read-only;
+			};
+			partition@0x00100000 {
+				label = "file-system";
+				reg = <0x00100000 0x01f00000>;
+			};
+			partition@0x02000000 {
+				label = "boot-config";
+				reg = <0x02000000 0x00100000>;
+			};
+			partition@0x02100000 {
+				label = "space";
+				reg = <0x02100000 0x01f00000>;
+			};
+                };
+        };
+
 	soc8548@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -59,6 +152,7 @@
 		ranges = <0x00000000 0xe0000000 0x00100000>;
 		reg = <0xe0000000 0x00001000>;	// CCSRBAR
 		bus-frequency = <0>;
+		compatible = "simple-bus";
 
 		memory-controller@2000 {
 			compatible = "fsl,8548-memory-controller";