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authorTimur Tabi <timur@freescale.com>2011-06-23 14:48:54 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-06-27 08:36:16 -0500
commit7b93eccf2876ba3b1c10dae22ca864a0eb08de4f (patch)
treed3afaa61a0e162eace990d7621a8949d4ae7291a /arch/powerpc/configs
parentebf714ff37561331eb39963945d80bfc2a59e00f (diff)
powerpc/85xx: clamp the P1022DS DIU pixel clock to allowed values
To ensure that the DIU pixel clock will not be set to an invalid value, clamp the PXCLK divider to the allowed range (2-255). This also acts as a limiter for the pixel clock. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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